Develop testbenches, testcases, and verification components using SystemVerilog and UVM. PCIe, Ethernet, AMBA protocols must. Create and execute detailed verification plans based on design specifications Drive coverage closure, and debug failures.
Male candidate managing day-to-day office operations, overseeing office maintenance, and facility management. Organized, proactive, comfortable with flexible working hours. Coordinating with the finance, IT, HR operations and Engineering teams.
We are seeking a dynamic HR to take ownership of core HR functions including Operations, Employee Engagement, Onboarding, Induction Training, and Performance Management. This is a people-oriented HR professional who has grown through the ranks in IT.
Candidates with 1-3 Yrs expertise in SV, UVM, Verilog, DV, RTL design knowledge. Preferred VLSI Diploma course mandatory.
Candidates with 1-3 Yrs expertise in SV, UVM, Verilog, DV, RTL design knowledge. Preferred VLSI Diploma course mandatory. VLSI products and services
Candidates with 1-3 Yrs expertise in SV, UVM, Verilog, DV, RTL design knowledge. Preferred VLSI Diploma course mandatory. VLSI products and services