Formal Verification Engineer

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About this opportunity

We are seeking a highly skilled and passionate Formal Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Key Responsibilities:

• Contribute to Formal Verification applying and evangelizing state of the art Formal Verification Methodologies across IP-level, subsystem-level and SOC Level.
• Collaborate with Architecture and Design teams to develop formal specifications and implementations.
• Define formal verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques.
• Develop comprehensive formal test plans, including unique security requirement verification.
• Build reusable and scalable formal verification environments and deploy relevant tools.
• Evaluate and recommend EDA solutions for Formal Verification and drive improvements to methodologies and flows.
• Debug complex issues in RTL designs based on formal results and contribute to design improvements.

Required Skills:

1. Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
2. Experience writing formal properties using System Verilog Assertions (SVA) or Property Specification Language (PSL).
3. Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques.
4. Fluency in hardware description languages, such as SystemVerilog.
5. Proficiency in scripting languages such as Python, Perl, or Tcl within Unix/Linux environments.

Education:

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.

Experience:

5+ years of experience in Design Verification, with at least 1 year in Formal Verification.

QFocus AI Pvt Ltd is an Equal Employment Opportunity employer.