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Formal Verification Engineer

Formal Verification Engineer

Accenture

4 - 9 years

5 - 9 Lacs

bengaluru

Posted:2 hours ago| Platform:

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Skills Required

formal verification engineer formal verification strategy development technical leadership model checking soc design leadership debugging electrical engineering uvm architecture

Work Mode

Work from Office

Job Type

Full Time

Job Description

About The Role

Project Role :Formal Verification Engineer

Project Role Description :Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.
Must have skills :SoC Verification

Good to have skills :NA
Minimum 7.5 year(s) of experience is required

Educational Qualification :15 years full time education
________________________________________SummaryWe are seeking top-tier Chip Verification Engineers with a strong passion for excellence in verification. The role involves working on cutting-edge SoC designs and ensuring functional correctness through rigorous verification processes. Candidates should have 4+ years of experience, with opportunities for engineers across experience ranges:4–7 years, 7–10 years, and 10+ years.Roles & Responsibilities

Drive the full chip verification cycle, including:oTest planning and strategy development.oWriting verification code and creating test scenarios.oPerforming tests and RTL debugging.oAchieving verification closure.

Collaborate closely with design engineers to debug and deliver functionally correct design blocks.

Develop and maintain verification components and environments using standard methodologies.

Ensure high-quality deliverables and adherence to project timelines.Professional & Technical Skills

Core Requirement:Exceptional verification expertise and problem-solving skills.

Technical
Skills:

oStrong experience in SystemVerilog/UVM or Specman/E.oHands-on experience in full-chip verification of large SoC chips (preferred).oProficiency in creating reusable verification components and environments.Solid understanding of SoC architecture and design principles.

Ability to work in a fast-paced environment and deliver high-quality results.
Additional Information

Experience Range:4+ years (ideal ranges:4–7, 7–10, and 10+ years).

Location:[Insert location or remote options if applicable].

Education:Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

Preferred:Prior experience with large-scale SoC projects and advanced verification methodologies.

Growth opportunities for engineers who demonstrate technical leadership and innovation.
Qualification 15 years full time education

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Formal Verification Engineer