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Accenture
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Formal Verification Engineer

Formal Verification Engineer

Accenture

2 - 5 years

5 - 9 Lacs

bengaluru

Posted:2 hours ago| Platform:

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Skills Required

formal verification engineer python soc design verification ovm uvm verilog debugging tools scripting formal verification model checking shell design debugging perl

Work Mode

Work from Office

Job Type

Full Time

Job Description

About The Role

Project Role :Formal Verification Engineer

Project Role Description :Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.
Must have skills :SoC Verification

Good to have skills :NA
Minimum 15 year(s) of experience is required

Educational Qualification :15 years full time education
Summary:Minimum of 15 years of experience, with demonstrated experience in design verification on complex projects in a leading chipset company.
SummaryRoles & Responsibilities

Strong knowledge with ASIC simulation tool & verification languages:all sign-off simulators, waveform debugging tools like Simvision / Verdi

Fluent in verification language such as UVM/OVM/RVM/System Verilog, Vera, Verilog

Experience in writing test-plans and creating directed and random test cases

Strong scripting skills in Perl, Python, shell etc.

Strong problem-solving skill to quickly identify and provide solution under tight schedule pressureProfessional & Technical Skills

Experience in low power verification using UPF or AMS/DMS is a plus Education:BE
Additional Information

Experience with verification of DSP based / RF designs at IP and / or subsystem level strongly preferred
Qualification 15 years full time education

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Formal Verification Engineer