Formal Verification Engineer

Summary

We are seeking top-tier Chip Verification Engineers with a strong passion for excellence in verification. The role involves working on cutting-edge SoC designs and ensuring functional correctness through rigorous verification processes. Candidates should have 4+ years of experience, with opportunities for engineers across experience ranges: 47 years, 7–10 years, and 10+ years

Roles & Responsibilities

• Drive the full chip verification cycle, including:

• Test planning and strategy development.

• Writing verification code and creating test scenarios.

• Performing tests and RTL debugging.

• Achieving verification closure.

• Collaborate closely with design engineers to debug and deliver functionally correct design blocks.

• Develop and maintain verification components and environments using standard methodologies.

• Ensure high-quality deliverables and adherence to project timelines.

Professional & Technical Skills

• Core Requirement: Exceptional verification expertise and problem-solving skills.

• Technical Skills:

• Strong experience in SystemVerilog/UVM or Specman/E.

• Hands-on experience in full-chip verification of large SoC chips (preferred).

• Proficiency in creating reusable verification components and environments.Solid understanding of SoC architecture and design principles.

• Ability to work in a fast-paced environment and deliver high-quality results.

Additional Information

• Experience Range: 4+ years (ideal ranges: 4–7, 7–10, and 10+ years).

• Location: [Insert location or remote options if applicable].

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

• Preferred: Prior experience with large-scale SoC projects and advanced verification methodologies.

• Growth opportunities for engineers who demonstrate technical leadership and innovation.Role & responsibilities

Preferred candidate profile