42 Soc Architecture Jobs

As a SoC Power Management Design Engineer at AMD, your role will involve developing and designing custom silicon for gaming consoles, datacenter, client, or embedded computer vision SOCs and related platforms. You will collaborate with the lead SoC architect to define customer-specific architectures, contribute to product specifications, and make performance and power trade-offs. Your work will span from early concept development through final production, requiring excellent organization and communication skills. You will work with expert architects and designers globally, presenting your findings to colleagues and customer engineering teams. Key Responsibilities: - Drive physical design and power architecture based on customer-specific requirements - Collaborate with AMD's Engineering teams and IP teams to aid in integration, implementation, and optimization of designs - Analyze power consumption and delivery using static, dynamic models, and emulation data - Evaluate performance across voltages for DVFS states of IPs, including inference engines, CPUs, Graphics, memory controllers, peripheral interfaces, caches, and network-on-chip fabric - Establish voltage-frequency design points in collaboration with technology teams, silicon validation, and product engineering teams - Define definitions for on-die PDN, power gating, package, and system power delivery in coordination with systems and architecture team - Analyze effects of control algorithms for management throttling mechanisms to optimize performance within thermal and peak current limits Preferred Experience: - Solid understanding of SoC construction, including fabric connectivity, memory systems, power delivery, clock distribution, floor planning, and packaging - Strong knowledge of SoC power management, power dissipation, and mobile battery life - Proficiency in scripting, data analysis, EDA tools, physical design tools for power optimization, VLSI design flow, and CMOS technology - Ability to model thermal control loops and throttling mechanisms - Strong problem-solving, organizational, and communication skills with the ability to work in a dynamic and diverse environment - Proficiency in scripting languages, particularly Python, is highly preferred - Experience with Power Architect, Power Artist, and VisualSim is a plus - Detail-oriented thinking skills and ability to tackle novel problems from different perspectives and levels of abstraction - Capability to analyze and streamline sophisticated workflows and processes through innovative automation Academic Credentials: - Bachelors or Masters degree in computer engineering/Electrical Engineering (Note: The benefits offered are described separately in the AMD benefits overview.),

You will be a part of an automotive client and will have the responsibility to handle various technical aspects related to SDV Enablers, Zonal Network, high-performance central compute modules, automated driving, AI, machine learning, perception modules, connected mobility, MLOps, and OTA updates. Your technical experience will include working with SoC architecture such as Qualcomm SA8650, Renesas RCAR, Nvidia Orin, TI, MobilEye, and SoC hardware like Ethernet, USB, UFS, Display Port, PCIe, QUP, UART, SPI, I2C, Camera, CPU Kryo, ARM Cortex R-52, Hexagon Tensor Processor, DDR, Flash ROM, and more. Additionally, you will handle software aspects including POSIX OS, QNX, middleware, hypervisor, and AD/ADAS technology stacks. You should have a good understanding of ADAS Features, Classic and Adaptive AUTOSAR software architecture, Continuous Integration, Continuous Delivery, CPU/GPU architectures, data structures, OS internals, multi-threading, memory management techniques, BSP porting, and device driver internals. Familiarity with V-Model, ASPICE, MISRA, ISO26262, Cybersecurity, Agile framework, crypto algorithms, cryptographic authentication method, and the ability to read schematics, electrical block diagrams, and IC datasheets is crucial. Your educational background should include a Bachelor or Masters degree in Computer Science or Electrical Engineering. You are expected to have a minimum of 7 years of experience, with at least 3 years in SoC platform development and 4+ years in automotive, AD/ADAS, or other embedded system low-level domains. As a part of your job responsibilities, you will lead, build, and mentor engineers working on sub-project activities. You should be comfortable working independently with minimal direction and possess strong verbal and written communication skills. Experience with PCs and application software like MS Office tools is also necessary. The job may require you to sit or stand for long periods and occasionally lift up to 25 pounds. Travel, both domestic and international, may be required based on project needs. In addition to the technical aspects, the company GlobalLogic offers a culture of caring, continuous learning and development opportunities, interesting and meaningful work, work-life balance, and a high-trust environment. As a trusted digital engineering partner to leading companies globally, GlobalLogic collaborates with clients to transform businesses and redefine industries through intelligent products, platforms, and services.,

You will collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Your responsibility will include owning end-to-end SOC RTL delivery while analyzing and optimizing design for power, performance, and area (PPA) targets. You will influence SoC definition, features, and adopt physical design friendly partitioning. Leading RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains will be a key aspect of your role. Demonstrating strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA) is essential. You will drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Designing and integrating standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 will also be part of your responsibilities. Engaging cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery is crucial. Supporting post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams, will be part of your regular tasks. Continuously evaluating and adopting new design methodologies and best practices to improve productivity and shift-left the design cycle is expected from you. Mentoring junior engineers, reviewing their work, and providing technical leadership and guidance across multiple design projects will be an important aspect of your role. You will also provide overall leadership and tracking of the team's goals. Contributing to the innovation quotient of the team via Design Patents, Industry Standard Publications, AI-enabled design methodologies, etc., will be an integral part of your responsibilities. To qualify for this position, you should have an M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture is essential. A strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems is required. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis is necessary. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks is also important. Excellent leadership, communication, and project management skills are desired, along with experience working with global cross-functional teams.,

As an FPGA Architect at NEC Corporation India Pvt. Ltd, you will be responsible for designing and implementing high-performance FPGA designs for wireless communication and aerospace systems. You will conduct research and development activities related to logical synthesis, netlist partitioning, placement, and routing optimizations for FPGA prototyping. Your role will involve optimizing FPGA designs for latency, throughput, power, performance, and area efficiency. Additionally, you will evaluate and select appropriate technologies and tools to support the development process, collaborating with cross-functional teams to align on product requirements and technical specifications. You should possess a BE/B.Tech/M.E/M.Tech or equivalent qualification with at least 12 years of experience in the field. Strong knowledge of SoC architecture, including CPU, GPU, memory hierarchy, interconnects, and accelerators is essential. Hands-on experience in hardware simulators, SoC design, RTL coding in Verilog/VHDL, and advanced digital verification methodology is required. Prior experience in integrating various components such as Nios, MPIS, MicroBlaze, ARM Cortex, GTX/GTH transceivers, and 10GE MAC/DMA controller/PCIe is preferred. Familiarity with EDA tools like Xilinx Vivado, SystemGenerator, ModelSim/QuestaSim, and proficiency in MATLAB and Python for modeling, simulation, and analysis are also desired. In this role, you will be responsible for improving or developing new products, components, equipment, systems, technologies, or processes. This may involve ensuring that research and design methodologies meet established scientific and engineering standards, formulating business plans and budgets for product development, analyzing quality/safety test results for compliance, and staying updated on industry developments for organizational and customer benefit. You may also be involved in technical presentations, monitoring product development outcomes, and managing product regulatory approval processes. As a senior-level professional, you will apply advanced knowledge and work independently to achieve results in overseeing and managing projects/processes with limited supervision. You will face difficult and sometimes complex problems, coaching and reviewing the work of lower-level professionals. NEC Corporation, a global leader in IT and network technologies with over 123 years of expertise, is committed to empowering people, businesses, and society. NEC India has been instrumental in India's digitization journey for the past 70 years, offering diverse solutions across various sectors. Headquartered in New Delhi, NEC India has a nationwide presence with branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida, and Surat. The company specializes in IT & Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. By deploying cutting-edge technology, NEC India aims to make lives easier, safer, and more productive for all, contributing to a brighter future.,

As an FPGA prototyping Engineer with more than 10 years of experience, you will be responsible for independently working on FPGA prototyping tasks. You should be proficient in modifying verilog models and incorporating glue logic adjustments to match the FPGA system requirements. It is essential for you to conduct simulations in the FPGA test bench to ensure the basic quality checks are met before finalizing the bit stream. Your role also involves providing support to the FW team during the debugging process. Your key responsibilities will include generating FPGA bit files by designing or modifying verilog models and integrating them into the SOC design. You will be expected to independently debug issues related to FPGA synthesis and utilize or customize the FPGA test bench for running simulations to verify basic functionality. Furthermore, you will collaborate closely with the FW team to offer debug support and work with the design and DV team for identifying and resolving issues. It is crucial for you to maintain clear documentation outlining the steps involved in the FPGA build and testbench setup. The ideal candidate will possess a strong understanding of FPGA architecture, synthesis, place and route, timing closure, and relevant tools such as Vivaldo. Previous experience working with HAPS boards, proficiency in Verilog for model modifications, and knowledge of SoC architecture, AHB bus protocols, DDR controller, MIPI protocol, and I2C protocol are essential requirements. Additionally, experience in debugging hardware and software issues, along with excellent communication and collaboration skills to effectively engage with cross-functional teams, will be beneficial for success in this role.,

Experience in modeling CPU, IP, or SoC components. Strong programming skills in C/C++, with a solid grasp of object-oriented design and debugging techniques. Good understanding of computer architecture fundamentals such virtual memory system, exceptions, and cache systems. Fast learner with the ability to work independently and adapt to complex technical domains. Exposure to ARM architecture or familiarity with ARM-based system design. Experience working with simulation environments or modeling frameworks (e.g., SystemC, TLM, Fast Models). Academic background in Computer Science or a related field (B.E./B.Tech./M.Tech. preferred). Knowledge of scripting languages (Python, Shell) for automation or test setup is a plus.

We are seeking a skilled Embedded SystemC Architect with over 10 years of experience to take charge of designing and developing high-performance virtual platforms and system-level models in Bangalore. As an Embedded SystemC Architect, you will play a crucial role in creating SystemC/TLM 2.0 models for various SoC components and virtual platforms, along with developing and enhancing embedded software and firmware elements in C/C++. Your expertise in SystemC modeling, SoC architecture, and solving intricate hardware-software interaction issues will be pivotal in this position. Your responsibilities will include designing and implementing SystemC/TLM 2.0 models for SoC components and virtual platforms, creating and managing embedded software and firmware components in C/C++, optimizing models for CPU, memory subsystems, hardware accelerators, and bus protocols, modeling peripherals such as Timers, DMA Controllers, and I/O devices, collaborating with hardware and software teams for co-simulation and integration, as well as mentoring junior engineers and leading technical discussions related to modeling and simulation. Key Requirements: - Proficiency in SystemC and TLM 2.0. - Strong command over C/C++ programming with a profound knowledge of Object-Oriented Programming (OOPS). - Hands-on experience in embedded software/firmware development. - Extensive understanding of SoC architecture, including CPU pipelines, GPUs, memory controllers and subsystems, hardware accelerators, and bus protocols (AXI, PCIe, USB). - Experience in modeling embedded peripherals. - Exposure to PSoc programming. Desired Skills: - Previous experience in developing Virtual Platforms (VPs) for semiconductor or embedded products. - Familiarity with simulators like QEMU, Synopsys Virtualizer, or equivalents. - Knowledge of hardware/software co-simulation methods. - Understanding of Verilog/SystemVerilog for hardware design analysis. If you are passionate about embedded systems, SystemC modeling, and SoC architecture, and possess a strong technical background in the mentioned areas, we encourage you to apply for this challenging and rewarding role as an Embedded SystemC Architect.,

The ideal candidate for the position of C++ Developer should hold a Bachelor's degree in computer science or a related program, or possess equivalent work experience. The candidate must demonstrate a high level of proficiency in C++11 and Linux system programming, including skills in IPC multi-processing, multi-threading, and debugging/core dump analysis. Additionally, the candidate should have strong debugging skills and knowledge of video streaming technologies such as MPEG-DASH, HLS, and Progressive Download. Moreover, familiarity with different audio/video formats like h264, H265, AV1, mp4, cmaf, ts, and tools for analyzing them is essential. Knowledge of SoC architecture and experience in developing firmware for hardware media pipelines are also required. The candidate should possess good communication skills, problem-solving abilities, and be a team player. Desirable qualifications include expertise in Digital Rights Management (Widevine, Playready, FairPlay) and Trusted Execution Environment, as well as knowledge of multimedia frameworks like gstreamer and ffmpeg. Experience in Web playback technologies such as MSE and EME is considered a plus. The responsibilities for this role include the development of firmware for hardware media pipelines, debugging, and analyzing core dumps. The candidate will work collaboratively within a team environment to deliver high-quality solutions. At GlobalLogic, we provide a culture of caring that prioritizes an inclusive environment where individuals are valued and supported. Continuous learning and development opportunities are offered to help employees grow both personally and professionally. Employees have the chance to work on meaningful projects that have a real impact on clients worldwide, fostering curiosity and problem-solving skills. The company values work-life balance and offers various career paths and work arrangements to achieve this balance. GlobalLogic is a high-trust organization that upholds integrity and ethical practices, providing a safe and reliable environment for employees and clients. GlobalLogic, a Hitachi Group Company, is a digital engineering partner to leading companies worldwide. With a focus on creating innovative digital products and experiences, GlobalLogic collaborates with clients to transform businesses and redefine industries through intelligent solutions.,

As a Senior Embedded Systems Engineer specializing in DDR (Double Data Rate) and LPDDR (Low Power Double Data Rate) memory technologies, you will be responsible for designing, developing, optimizing, and debugging memory subsystems for embedded platforms. Your role will involve architecting and developing DDR/LPDDR memory controllers, working on memory initialization, configuration, and tuning, analyzing and optimizing latency, bandwidth, and power consumption, as well as implementing error detection and correction mechanisms for reliability. You will also be tasked with debugging memory timing issues, bus contention, and signal integrity problems using oscilloscope and logic analyzers, optimizing memory access patterns to enhance overall system throughput, and developing power management techniques for LPDDR to optimize energy efficiency in low-power embedded systems. Additionally, you will work on developing low-level firmware, bootloader configurations, and memory initialization scripts for embedded platforms, implementing memory drivers in C/C++ for real-time operating systems (RTOS) or bare-metal environments, and collaborating with software teams to integrate memory controller firmware into embedded applications. In this role, you will collaborate with hardware engineers for PCB design, memory routing, and signal integrity analysis, perform hardware bring-up and validation of DDR/LPDDR components, work with SoC vendors and memory manufacturers to ensure compatibility and performance compliance, and develop and execute memory stress tests to validate reliability under different conditions. You will also use JTAG, debuggers, and oscilloscopes to troubleshoot and analyze memory-related issues and perform thermal and power analysis to ensure compliance with design specifications. The ideal candidate for this position should have a strong expertise in DDR/LPDDR memory technologies, including LPDDR2/LPDDR3/LPDDR4/LPDDR5, in-depth knowledge of memory controllers, PHY, DRAM refresh mechanisms, and clock synchronization, proficiency in low-level programming (C, C++) for embedded systems, experience with real-time operating systems (RTOS) such as FreeRTOS, QNX, or VxWorks, and an understanding of memory power management techniques for mobile and battery-powered devices. Additionally, hands-on experience with memory performance benchmarking tools and techniques, experience in debugging tools such as JTAG, Lauterbach, and oscilloscopes, and familiarity with SoC architecture, ARM processors, and bus protocols (AXI, AHB, SPI, I2C, PCIe) are desired skills. Soft skills such as strong problem-solving and analytical skills, excellent communication and documentation skills, ability to work collaboratively in cross-functional teams, attention to detail, and a proactive approach to debugging and optimization are also important for this role. Preferred qualifications include experience with high-speed PCB layout and signal integrity analysis tools, knowledge of AI/ML-based memory optimization techniques, familiarity with secure boot and memory encryption mechanisms, and prior experience working with memory manufacturers (Samsung, Micron, SK Hynix, etc.). This role offers the opportunity to work on cutting-edge embedded memory technologies, optimizing DDR/LPDDR performance for next-generation devices. You will collaborate with industry experts, tackle complex system challenges, and contribute to innovative solutions in high-performance and low-power computing.,

Are you ready for a new and exciting challenge If you are a self-motivated SoC Verification Engineer with expertise in SoC architecture and looking to make a difference in an innovative and inclusive team, you've come to the right place! We are seeking a highly skilled and experienced SoC validation expert to join our growing team. The ideal candidate will be working on various industry-based like mobile, server etc. System on Chip (SoC) designs containing custom hardware subsystem and transactors. This challenging position will offer you the opportunity to work with Synopsys advanced technology in a collaborative environment. Responsibilities include developing validation environment on various industry-based SoC design on Emulation/FPGA and/or Virtual environments, collaborating with Design SoC, Solutions and Synopsys IP team, aligning with the development work across multiple teams, staying up to date with the latest advancements in semiconductor design and Emulation technology, mentoring junior engineers and team members, and working with engineering teams to improve various workloads. The position is based in Bengaluru and requires 6 to 10 years of experience. Required Skills & Experience: - Bachelors or masters in electronic engineering, Electrical Engineering, Computer Engineering, VLSI, or related field. - Minimum 6 years in SoC Validation. - Emulation experience in Zebu/Haps or equivalent platforms. - HW RTL verification and debugging expertise. - Design & Develop test environment having various debug hooks and automation. - Knowledge/experience in high-speed protocols such as USB, PCIe, UFS, or LPDDR technology is a plus. - Able to work independently with minimal supervision, Lead the team technically, capable of mentoring and developing a strong team. Nice To Have Skills & Experience: - Excellent communication (written, verbal, presentation) skills. - Proven track record of generating consistent, complete, and concise written specifications. - Motivated to continuously develop skills, development processes, and improve results.,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, digital/analog/RF/optical systems, equipment and packaging, test systems, FPGA, and DSP systems to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements effectively. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 8+ years of Hardware Engineering experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 7+ years of Hardware Engineering experience OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of Hardware Engineering experience As a design verification engineer, you will work within an Integrated Wireless Technology (IEEE 802.11) team, embedded into an ARM-based SOC infrastructure. Responsibilities include developing HW blocks, conducting design reviews, and delivering IPs to the Subsystem team for complex SoCs. You will play a critical role in the WLAN subsystem, contribute to IP design, and sign-off the core to the SOC design team. Skills/Experience: - 6-15 years of experience in Digital Design with a leading chipset company - Proficient in Wireless connectivity technologies: IEEE 802.11 a/b/g/n/ac/ax/be - Knowledge in SoC architecture, including ARM CPUs, communications peripherals, clocking, bus structures, and power management - Strong fundamentals in areas such as Wireless and Mobile communications, Information theory, Signal processing - Expertise in fixed-point implementation concepts like Truncation, Rounding, Saturation - In-depth knowledge of Digital communication engines like Demodulator, Deinterleaver, Viterbi/Turbo Decoders, Sigma-Delta modulation, FFT, etc. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application/hiring process. Applicants can request reasonable accommodations by contacting disability-accommodations@qualcomm.com. Employees are expected to adhere to all applicable policies and procedures, including security measures regarding protection of confidential information. For more information about this role, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is looking for an experienced individual with a strong knowledge of digital design and SOC architecture. You should have a good understanding of OOP concepts and hands-on experience in HVL such as System Verilog, UVM/OVM & System C, as well as in HDL such as Verilog. Knowledge of ARM/DSP CPU architecture and High-Speed Peripherals like USB2/3, PCIE, or Audio/Multimedia is essential for this role. Additionally, familiarity with Power-aware Verification, GLS, and Test vector generation would be a plus. Exposure to Version managers like Clearcase/perforce and proficiency in scripting languages like Perl, Tcl, or Python are desired skills. Analytical and debugging skills are also required to excel in this position. The ideal candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 2+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in a related field would also be considered. With 3-6 years of experience and a Bachelor's or Master's degree in Engineering, you will be well-suited for this role at Qualcomm India Private Limited. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require assistance, you can reach out to disability-accommodations@qualcomm.com or Qualcomm's toll-free number. It is important for Qualcomm employees to adhere to all applicable policies and procedures, especially regarding the protection of confidential information. Staffing and recruiting agencies are advised that Qualcomm's Careers Site is solely for individuals seeking employment opportunities at Qualcomm. Unsolicited submissions from agencies will not be entertained, and Qualcomm does not accept unsolicited resumes or applications. For more information about this role, please contact Qualcomm Careers.,

You are invited to join our team at Sandisk as a DFT Engineer, where you will play a crucial role in developing the next-generation Flash Controllers. As an SoC DFT Engineer, your primary responsibility will be to define and implement cutting-edge DFT solutions, focusing on SCAN, MBIST, BSDL, and other key aspects. The ideal candidate should possess a profound understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG, and Simulation expertise. As a DFT Engineer at Sandisk, you will be involved in various essential duties and responsibilities, including: - Defining DFT Architecture for SoC development. - Leading complex activities and offering solutions for intricate DFT problems. - Collaborating with cross-functional teams to establish and refine SoC DFT requirements in alignment with industry standards and customer needs. - Working closely with Design, Verification, Physical Design, and Test Engineering teams to guide them on test requirements and methodologies. - Collaborating with the Product Engineering team to comprehend test requirements and participating in complex silicon debugs. - Evaluating all aspects of the SoC DFT flow from requirements to detailed definitions and continuously improving the DFT methodology in collaboration with CAD. Qualifications: - B.Tech / M.Tech / Ph.D. in Electronics, Computer Science, or Electrical Engineering. - Minimum of 15+ years of experience in DFT. - Strong understanding of DFT Architecture. Key Skills: - Extensive experience in SoC DFT architecture, DFT IP development, and DFT methodology. - Proven track record of driving DFT architecture in complex ASIC designs. - Ability to work independently on multiple complex DFT problems across different projects. - Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs). - Proficiency in SCAN, MBIST implementation. - Solid understanding of JTAG & BSDL standards. - Good understanding of Test clocking requirements, Test mode timing closure. - Proficiency in complex silicon debugs and yield analysis. - Solid understanding of SoC architecture and low-power design principles. - Understanding of High-Speed interfaces (PCIe or UFS protocols) and experience with SSD/Flash is an advantage. - Excellent analytical and problem-solving skills. - Strong communication skills and the ability to work effectively in cross-functional teams. At Sandisk, we value diversity and believe that a diverse workforce leads to the best outcomes for our employees, customers, and communities. We are committed to creating an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution. Additionally, we offer opportunities to applicants with disabilities and ensure a smooth navigation of our careers website and hiring process. If you require any accommodations during the application process, please reach out to us at jobs.accommodations@sandisk.com with details of your request, the job title, and requisition number.,

As an experienced professional in Electrical Engineering or Electronics and Communication, you will be responsible for defining and driving System-on-Chip (SoC) Architecture while conducting thorough Power, Performance, and Area (PPA) trade-off analysis. Your role will involve leading the selection and integration strategies of IPs for performance-driven designs. Additionally, you will be tasked with architecting and reviewing Mixed Signal Designs and Multi-core Processor Subsystems. Collaboration is key in this role as you will work closely with RTL to Physical Design teams to ensure high-quality deliverables and coordinate with Physical Design (PD) teams for successful Tapeout activities. It will be your responsibility to ensure that the architectural decisions align with foundry node requirements across various technology nodes such as 28nm, 16nm, 7nm, and others. To excel in this position, you should have a minimum of 18 years of experience post Engineering degree, with a demonstrated track record in SoC design methodologies and architecture definition. A deep understanding of RTL development, integration, and backend handoff is essential. Your cross-functional collaboration skills will be put to the test as you engage with analog, PD, DFT, and software teams. Exposure to foundry-specific constraints and best practices across different technology nodes will be an advantage. If you are looking for a challenging yet rewarding opportunity to contribute your expertise in SoC architecture and design methodologies, this role offers a platform for you to showcase your skills and make a significant impact in the semiconductor industry.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group, specifically in the Hardware Engineering department. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other hardware components to contribute to the development of cutting-edge products. Collaboration with cross-functional teams is essential to ensure that solutions meet performance requirements. The ideal candidate should possess a Bachelor's, Master's, or PhD degree in Computer Science, Electrical/Electronics Engineering, or a related field, along with 2+ to 4+ years of experience in Hardware Engineering. The role involves working on Qualcomm Snapdragon CPUSS Architecture and performance team, where tasks include analyzing performance aspects, guiding execution teams, driving deep-dive performance analysis, and providing solutions for CPU subsystem and related SOC Modules. Candidates should have a strong background in CPU architecture/analysis, knowledge of ARM processors, familiarity with microprocessor and/or SoC architecture, experience with workload performance characterization, and hands-on experience with debug environments and emulation platforms. Additionally, experience with industry standard benchmarks, Linux, Android internals, and programming languages such as C/C++, Perl, or Python is beneficial. Applicants are expected to have excellent communication skills, the ability to collaborate effectively, and a keen interest in investigating anomalies and identifying performance trends. Familiarity with pre-silicon environments, post-silicon experience, and debugging tools is advantageous for this role. If you have a Bachelor's degree in Electrical, Electronics, or Computer Engineering, with 6+ years of experience in SOC/CPU post-silicon validation/performance analysis, and possess a strong knowledge of modern OS kernels (Android, Linux), this role might be suitable for you. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations to individuals with disabilities throughout the application/hiring process. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. If you are interested in this role, contact Qualcomm Careers for more information.,

As a SystemC Architect, you will be responsible for architecting and developing high-performance SystemC/TLM 2.0 models for complex SoC systems. Your role will involve designing and implementing simulation models for embedded systems and hardware components, including CPUs, GPUs, accelerators, and memory subsystems. You will collaborate closely with cross-functional teams to define system architecture and interface requirements and lead performance optimization and validation efforts for virtual platforms. Additionally, you will mentor junior engineers and drive technical excellence within the team. To excel in this role, you must have expertise in SystemC and Transaction-Level Modeling (TLM 2.0) along with strong proficiency in C/C++ programming and a deep understanding of Object-Oriented Programming (OOP). Your hands-on experience in embedded software/firmware development and solid knowledge of SoC architecture, including CPU pipelines, GPUs, hardware accelerators, memory hierarchies, and bus protocols (AXI, PCIe, USB, etc.) will be crucial for success. Experience in peripheral modeling such as timers, DMA controllers, and I/O devices is also required. Good-to-have skills for this position include experience in developing Virtual Platforms (VPs) for semiconductor applications, familiarity with simulators like QEMU, Synopsys Virtualizer, or similar tools, exposure to hardware/software co-simulation environments, and an understanding of Verilog/SystemVerilog for analyzing and correlating with hardware designs. If you have 10+ years of experience, a strong foundation in embedded systems, and the required skill set, we encourage you to apply for this challenging and rewarding SystemC Architect role based in Bangalore.,

As a Senior SOC Architect, you will play a crucial role in leading the design and evolution of our Security Operations Center (SOC) infrastructure and strategy. Your extensive expertise in security architecture, incident response frameworks, threat intelligence integration, and enterprise-grade SOC solutions will be essential for the success of this high-impact position. Your responsibilities will include designing and continually enhancing SOC architecture, processes, and automation frameworks. You will be responsible for evaluating and implementing various security technologies such as SIEM, SOAR, EDR, IDS/IPS, among others. Additionally, you will lead the integration of threat intelligence feeds, analytics, and response capabilities while ensuring alignment with business and compliance requirements such as ISO 27001 and NIST. In this role, you will provide strategic direction and architectural governance for SOC operations, mentoring SOC teams to ensure technology alignment with best practices. Collaboration with stakeholders, IT, and security leaders to define threat models and use cases will be a key aspect of your responsibilities. To be successful in this role, you should possess at least 10 years of experience in cybersecurity, with a minimum of 3 years in SOC architecture or design-focused leadership roles. Your proven experience in deploying and scaling SOC tools and platforms like Splunk, QRadar, Sentinel, Palo Alto XSOAR, and CrowdStrike will be valuable. A deep understanding of threat detection, incident response, security automation, network security, endpoint security, cloud security, and log management is essential. Familiarity with security frameworks and standards such as MITRE ATT&CK, NIST, and ISO is also required. Your exceptional leadership, communication, and documentation skills will be crucial for effectively fulfilling this role. This is a full-time on-site position located in Andheri East, Mumbai. The client interview process will consist of 5 rounds, with the first round being on-site and subsequent rounds conducted virtually. Join us as a Senior SOC Architect and be at the forefront of building a resilient and modern SOC capable of staying ahead of today's advanced threats.,

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise emulation / prototyping using Cadence / Synopsys tool flows Expertise in Palladium / Protium / HAPS / Zebu tools Expertise in System Verilog & Verilog language semantics and compilation flows Expertise on AXI protocol Good Knowledge on SOC architecture

Protect Threat is a trusted provider of advanced cybersecurity and IT services, empowering businesses to navigate today's evolving cyber landscape with confidence. Our mission is to protect organizations from threats, ensure compliance, and enable growth by delivering tailored cybersecurity strategies. We offer a comprehensive suite of services, including penetration testing, cloud security, threat intelligence, SOC-as-a-Service, and incident response, to safeguard digital assets and strengthen security posture. Protect Threat is seeking an experienced Security Operations Center (SOC) Architect / Consultant to help design, implement, and operationalize the SOC-as-a-Service offering. This is a contract consulting role with the potential for extension or transition into a long-term engagement based on project outcomes. The consultant will be responsible for setting up the SOC framework, tools, and processes to enable Protect Threat to deliver a scalable, multi-client SOC-as-a-Service. The role entails providing strategic guidance, hands-on technical execution, training internal teams, and guiding the evolution of managed SOC services. Key Responsibilities: - Assess organizational requirements and design a scalable SOC-as-a-Service architecture. - Recommend, deploy, and configure SIEM/SOAR solutions such as Wazuh, ELK, Splunk, QRadar, etc. - Define and implement incident response playbooks, escalation processes, and reporting frameworks. - Integrate log sources, threat intelligence feeds, and security automation workflows. - Ensure SOC operations align with industry standards and compliance frameworks like ISO 27001, PCI DSS, NIST, MITRE ATT&CK. - Provide knowledge transfer and training to internal teams for long-term SOC management. - Act as a trusted advisor, shaping Protect Threat's SOC-as-a-Service model and delivery capabilities. Qualifications: - Proven experience in SOC design, architecture, and consulting. - Strong expertise in SIEM, SOAR, log management, and security automation. - Knowledge of cybersecurity frameworks and compliance requirements. - Ability to work independently and deliver within contract timelines. - Excellent communication skills to engage with technical and business stakeholders. - Relevant certifications preferred (e.g., CISSP, CISM, CCSP, OSCP, SIEM-specific certifications). - Bachelor's or Master's degree in Cybersecurity, Information Technology, Computer Science, or related field. Engagement Details: - Engagement Type: Contract (initial consulting role) - Location: Remote / Hybrid (as per project needs) - Duration: Project-based (with possible extension) This role presents an excellent opportunity for a seasoned SOC professional who enjoys building security services from the ground up and wants to play a pivotal role in shaping Protect Threat's SOC-as-a-Service model. Interested consultants can apply directly here or share their profile at inquiries@protectthreat.com.,

Silicon Labs is the leading innovator in low-power wireless connectivity, dedicated to building embedded technology that connects devices and enhances lives. By incorporating cutting-edge technology into highly integrated SoCs, Silicon Labs empowers device manufacturers with the solutions, support, and ecosystems necessary for creating advanced edge connectivity applications. With operations in over 16 countries and headquartered in Austin, Texas, Silicon Labs is the trusted partner for innovative solutions in smart home, industrial IoT, and smart cities markets. Joining the team at Silicon Labs means being at the forefront of secure, intelligent wireless technology for a more connected world. As part of the team, you will play a critical role in defining platform requirements for scalable products targeting a wide range of IoT applications. Your responsibilities will include driving the architecture for a scalable compute platform, focusing on key technical areas such as core-compute architecture, high performance external memory interface, virtualization, isolation at SoC level, and more. To excel in this role, you will need to have a strong grasp of general SoC architecture, including boot, power management, clock & reset, debug & security. Experience in key architecture aspects like power estimation, die size estimation, and basic technology fundamentals will be crucial. You will be responsible for driving competitive analysis, product roadmaps, and ensuring clear mapping of the product portfolio to target applications. The ideal candidate will possess excellent communication skills to convey complex technical issues effectively and collaborate closely with cross-functional teams. You should be capable of translating high-level requirements into comprehensive product requirement documents and presenting technical overviews, competitive landscape analysis, and product positioning strategies. Minimum qualifications for this role include expertise in virtualization & isolation at the SoC level, a strong understanding of SoC architecture, experience in power estimation, and driving competitive analysis for product design and specifications. Additional qualifications such as full SoC flow know-how, hands-on experience in multiple functional areas, and business case analysis understanding will be considered a plus. As part of Silicon Labs, you will not only work with a highly skilled team where every engineer's contribution is valued, but you will also enjoy benefits such as Equity Rewards (RSUs), Employee Stock Purchase Plan (ESPP), insurance plans, National Pension Scheme (NPS), flexible work policies, childcare support, and a supportive work environment that promotes work-life balance and fun.,

As a candidate for this position, you should hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR) technology. Your responsibilities will include silicon bringup, functional validation, characterizing, and qualification, as well as working with board schematics, layout, and debug methodologies utilizing lab equipment. Preferred qualifications for this role include experience in hardware emulation with hardware/software integration, proficiency in coding languages such as Python for automation development, and experience in Register-Transfer Level (RTL) design, verification, or emulation. Knowledge of SoC architecture, boot flows, and HBM/DDR standards will be advantageous. In this role, you will contribute to shaping the future of AI/ML hardware acceleration by working on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's AI/ML applications. You will be part of a team dedicated to developing custom silicon solutions for Google's TPUs, with a focus on design and verification expertise related to TPU architecture and AI/ML-driven systems. Your primary responsibility will be the post-silicon validation of Cloud Tensor Processing Unit (TPU) projects. This will involve creating test plans and content for subsystem testing, verifying content on pre-silicon platforms, executing tests on post-silicon platforms, and debugging issues. Collaboration with engineers from various teams will be essential in validating functional, power, performance, and electrical characteristics of the Cloud TPU silicon to ensure high-quality designs for next-generation data center accelerators. The ML, Systems, & Cloud AI (MSCA) organization at Google is involved in designing, implementing, and managing hardware, software, machine learning, and systems infrastructure for Google services and Google Cloud. Your work will impact millions of users worldwide by prioritizing security, efficiency, and reliability in developing TPUs and running a global network. Your responsibilities will include developing and executing tests for memory controller High Bandwidth Memory (HBM) post-silicon validation, driving debugging efforts, ensuring validation coverage, and assisting in pre-silicon integration and validation on hardware emulators.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other components to develop cutting-edge products. You will collaborate with cross-functional teams to deliver solutions that meet performance requirements. The ideal candidate will have a strong background in CPU architecture and analysis, as well as experience with ARM/X86 chipsets and embedded system concepts. Minimum qualifications for this role include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience will also be considered. The selected candidate will work on Qualcomm Snapdragon CPUSS Architecture and performance team, analyzing performance aspects of Snapdragon CPU subsystem, guiding the execution team, and driving deep dive analysis on performance issues. Essential skills and experience for this position include familiarity with Microprocessor and/or SoC Architecture, ARM processor-based systems, cache configurations, workload performance characterization, and debugging skills in a bare-metal environment. The candidate should also have experience with Lauterbach debug environment, workload-driven investigations, and performance projections on silicon. Strong data analysis skills, programming experience, and knowledge of Linux and Android internals are desirable. Applicants should hold a Bachelor's degree in Electrical, Electronics, or Computer Engineering and/or Computer Science with at least 6 years of experience in SOC/CPU post-silicon validation/performance analysis. Strong knowledge of modern OS kernel (Android, Linux) is required for this role. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Overall, Qualcomm is looking for a candidate with a passion for hardware engineering, performance analysis, and system-level debugging, who can collaborate effectively with peers and senior engineers to drive innovation and excellence in product development.,

As a SOC Performance Modeling Engineer at AMD, you will be an integral part of the Client Performance Modeling Team based in Hyderabad, India. Your primary responsibility will involve analyzing the architectural performance of notebook and desktop processors through modeling and RTL simulation. By collaborating with SoC, IP & Model architects, you will evaluate and debug CPU/GFX/NPU processor performance and suggest architectural enhancements to drive innovation. To excel in this role, you should possess a deep passion for cutting-edge SoC architecture, digital design, and verification. Your effective communication skills and ability to work seamlessly with architects & engineers across different locations and time zones will be crucial. Strong analytical and problem-solving abilities are essential, coupled with a willingness to learn and tackle challenges head-on. Key responsibilities in this role include developing architectural models, tools, and infrastructure, optimizing performance features, proposing enhancements for next-gen SOCs, conducting trade-off studies for performance, power, and area, evaluating benchmarks for various processors, advancing simulation infrastructure and methodology, and providing technical guidance to the Client SoC team. The ideal candidate would have 3-15 years of industry/academic experience, expertise in computer system simulation and performance evaluation, familiarity with ASIC HW design and verification languages/tools such as Verilog, System Verilog, System C, OVM/OVC, proficiency in programming and scripting languages like C/C++, Perl, Python, and a track record of analyzing system bottlenecks to optimize computing systems for performance. Additionally, detailed microarchitecture knowledge of CPU, GPU, NPU, I/O subsystem, and/or DRAM controller would be advantageous. An academic background in Computer/Electrical Engineering with a Bachelor's or Master's degree is required to qualify for this position at AMD. Explore the AMD benefits at a glance to discover the comprehensive perks offered to our valued employees.,

You will be responsible for executing small to mid-size customer projects in various fields of VLSI Frontend Backend or Analog design with minimal supervision. As an individual contributor, you will work on tasks related to RTL Design/Module and provide support to junior engineers in Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your successful and on-time completion of assigned tasks will contribute to the quality delivery approved by the project lead/manager. Your outcomes will be measured based on the quality of deliverables verified by the Lead/Manager, timely delivery as per relevant metrics, reduction in cycle time and cost through innovative approaches, number of trainings attended, and the number of new projects handled. You are expected to ensure the quality of deliverables by facilitating clean delivery of designs and modules for easy integration at the top level, meeting functional specifications and design guidelines without any deviation, and documenting tasks and work performed. Timely delivery is crucial, meeting project timelines as requested and supporting the team lead in intermediate task delivery. Teamwork plays a significant role, requiring your participation in supporting team members/lead when needed and performing additional tasks in case any team member is unavailable. Embracing innovation and creativity, you should look to automate repeated tasks to save design cycle time, participate in technical discussions, and contribute to training forums. Your skills should include expertise in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, Makefile, and Spice, among others. Proficiency in EDA Tools like Cadence, Synopsys, Mentor tool sets, and technical knowledge in IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, Floorplan, Clocks, and more is required. Familiarity with CMOS FinFet, FDSOI, technology, strong communication, analytical reasoning, problem-solving skills, and the ability to learn new skills are essential for successful project execution. Your knowledge should span across Frontend/Backend/Analog Design, project experience in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, understanding of design flow, methodologies, technical specifications, and the ability to execute assigned tasks effectively based on client/manager requirements. Having a command over digital logic design concepts, experience in large IP block design, knowledge of Synopsys/Cadence/Mentor simulation tools, Perl/TCL scripting, RTL logic synthesis, and basic SOC architecture will be advantageous for this role. Your attention to detail, technical skills, and ability to deliver tasks on time with quality are crucial aspects in contributing to the success of projects at UST.,

We are seeking an experienced RTL Design Engineer to be a part of our advanced ASIC/SoC development team in Bengaluru. As an RTL Design Engineer, you will be responsible for developing high-quality, synthesizable RTL code using Verilog/SystemVerilog and integrating complex IPs and subsystems into high-performance SoCs. Collaboration with system architects, contribution to micro-architecture, and ensuring design quality through checks like Lint, CDC, and Synthesis will be key aspects of this role. Your responsibilities will include leading SoC-level integration activities, providing technical guidance in design reviews, and interfacing with cross-functional teams for smooth bring-up and signoff processes. The ideal candidate should possess a Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, along with at least 7 years of experience in RTL design and SoC integration. Strong skills in Verilog/SystemVerilog, knowledge of SoC architecture and bus protocols, and proficiency in industry tools like Design Compiler, Spyglass, and VCS are essential for this role. If you have a deep understanding of clock/reset strategies, hierarchical design practices, timing closure, synthesis flows, and constraints development, along with strong analytical and debugging skills to resolve complex RTL and integration issues, we would like to hear from you. Join us and contribute to the design, integration, and verification of cutting-edge IPs and subsystems within high-performance SoCs.,