10 Soc Architecture Jobs

Looking for someone who has very good exposure in Firmware (FW) and Software (SW) components of the HPC SoC to play a crucial role in designing and optimizing System-on-Chip (SoC) solutions for HPC applications. Responsibilities Architect and design SoC solutions for HPC applications, ensuring optimal performance and efficiency. Define firmware and software architecture for SoC components, including bootloaders, drivers, and system-level software. Collaborate with hardware teams to ensure seamless integration of FW/SW with SoC designs. Optimize power, performance, and area (PPA) trade-offs in SoC architecture. Decent exposure on ARM A and M latest profiles, PCIe, CXL,UCIe, NIC modules. Implementing Root Of Trust flow. Looking after BMC connectivity related requirements and working with team to implement them. Work on low-level programming , including embedded firmware development and OS kernel modifications . Lead debugging and validation efforts for SoC firmware and software. Stay updated with emerging technologies in HPC, SoC design, and software development. Qualifications Bachelor's, or Masters in CSE or ECE . Strong expertise in SoC architecture, firmware development, and software engineering . 10+ years of experience with HPC workloads, parallel computing, and memory management . Proficiency in C/C++, Python, and assembly programming . Knowledge of SoC interconnects, memory subsystems, and power management . Familiarity with Linux kernel development, RTOS, and embedded systems . Experience with hardware/software co-design and debugging tools . Familiarity of using benchmarking and performance tools Education Requirements: B. Tech / M. Tech (ECE / CSE) Experience: 10+ Years Location: Hyderabad Shift: General Work Week: Monday to Friday

NES SOC Architecture team is looking for an outstanding engineer to work on definition of NEX SoC(s) for Intel Server, Client and IoT platforms. In this role, you will develop and drives end-to-end SoC architecture for highly optimized, modular, and scalable SoC, based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle.You will collaborate across disciplines to analyze workloads, identify opportunities for improvement, determine priorities, and balance trade-offs. Responsibilities include: Determining functional requirements based on product goals, use cases, and workload analysis. Defining SoC architecture to meet product requirement and deliver architecture specifications. Evaluates feasibility trade-offs and explores and defines new approaches and novel architectures for SoC. Invents, conceptualizes, and specifies microarchitecture and architectural features for next-generation products to deliver optimized SoC for multiple segments from high performance computing to extreme low-power products. A successful candidate will demonstrate. Broad knowledge of SoC architecture. Performance, power trade-off understanding. Deep expertise in domains such as reset, clock, coherency, debug, power management, performance evaluation Exceptional communication skills. Collaborates with design engineers, system engineers, verification engineers, structural design engineersto improve the overall design of SoC and overcome constraints. Work will include a combination of individual contribution and leveraging team participation through mentoring and leadership of technical initiatives. Qualifications: Minimum Qualifications: Bachelor's degree or higher in Computer Science or Electronics Engineering, 15+ years relevant experience in Silicon development in Arch/Uarch, Modeling, Designincluding multiple project development life cycles with at least one as lead architect or lead u-architect.

Job Area: Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.Qualcomm's SoC Validation Team (SVE - System SOC/silicon Validation) is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The Validation team works closely with architects, designers, verification engineers, software engineers, and customers.We are looking for self-motivated engineers who will be part of bare-metal SoC validation team and will have the following responsibilities. Responsibilities Design, develop, debug system/IP validation framework to be used in bare-metal and light-weight-RTOS environment for SoC validation in one of the areas mentioned below Understand the SoC architecture, new features and prepare test plan Develop/port/enhance system validation content based on system level use cases, low power use cases, find HW bugs and root cause them Interface with Design/Verification/Software/Customer Engineering teams for test plan and debugs Interface with various IP validation team and cross functional teams(Design/Verification/SW) for test plan creation and debug complex issues Use silicon debug hooks to measure power/performance/coverage and other KPI metrics Manage a team of silicon validation team members Minimum Qualification : Bachelor's/Master"s degree in Electronics and Communication Engineering/Computer Science or related field 11+ years of working experience in SOC validation (Candidates with less experience with good academics from premier institutes can also be considered) Mandatory Skills: Good knowledge and understanding of Embedded SW architecture and development in C, C++, Assembly C language expertise for low level programming, assembly language for any processor, C-assembly interworking Hands on end to end experience in one or more of the IP validation flow from architecture review, testplan creation, testcases development, execution, debugsCPUSS, DDRSS, Multimedia (Camera, Video, Display, GPU) blocks Good Experience in working closely with Design/Verification/Arch/Customer Engineering teams for IP/SOC validation planning, execution and debugs Good knowledge of ARM/X86/PowerPC CPU architecture, Interrupt handling, Cache coherency, IO Coherency Good knowledge of SoC architecture having Multicore/Multiprocessor with SMP/heterogenous cores, memory management, CPU concepts Having experience of managing team members as people manager Compiler/LinkerProficient in using compilers and linkers such as GCC, CLANG, RVDS, LLVM, Experience in optimizing code and resolving linker issues to ensure efficient and error free builds Experience in using JTAG interfaces and tools for debugging SOC/silicon design issues Scripting languages such as Python, shell scripting etc. Desired Skills Exposure to SoC architecture paradigms " interconnects, power management, emulation(pre-Si) environment Exposure to working on emulation/pre-si environment is added advantage Experience working with boot code for ARM processors Knowledge of Operating systems/RTOS/Linux kernel internals, multithreading, scheduling policies/locking mechanism, Virtual memory/MMU/paging etc Software development for silicon enablement, silicon validation, design issue debugs Board Bring-up/Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs Exposure to build automationExperience with build automations tools such as Jenkins and experience in creating automated build pipelines to stream line the development process Exposure to Regression testingUnderstanding of the regression testing methodologies and tools. Ability to design, implement and execute comprehensive regression test suites to ensure software quality and stability Code ReviewsAbility to conduct thorough and constructive code reviews to maintain code quality, ensure best practices and identify the areas of improvements

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 7+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelors/ Masters degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

General Summary: Requirement: Looking for candidates with 2 to 6 years of work experience . Interview Details: 1st/2nd March. Invite only hiring drive for shortlisted candidates. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Qualcomm's SoC Validation Team (SVE - System Validation & Emulation) is part of the central SoC digital hardware organization responsible for the overall quality of the SoC silicon. The Validation team works closely with architects, designers, verification engineers, software engineers, and customers.We are looking for self-motivated engineers who will be part of bare-metal SoC validation team and will have the following responsibilities. Responsibilities Design, develop, debug system/IP validation framework to be used in bare-metal and light-weight-RTOS environment for SoC validation Understand the SoC architecture, new features and prepare test plan Develop/port/enhance system validation content based on system level use cases, low power use cases, find HW bugs and root cause them Interface with Design/Software teams for test plan and debugs Interface with various IP validation team and cross functional teams(Design/SW) for test plan creation and debug complex issues Use silicon debug hooks to measure power/performance/coverage and other KPI metrics Minimum Qualification : Bachelor's/Masters degree in Electronics and Communication Engineering/Computer Science or related field 2-5 years of working experience (Candidates with less experience with good academics from premier institutes can also be considered) Mandatory Skills: Good knowledge and understanding of Embedded SW architecture and development in C, C++, Assembly C language expertise for low level programming, assembly language for any processor, C-assembly interworking Good knowledge of ARMv8/ARMv9/x86/PowerPC CPU architecture, Interrupt handling, Cache coherency, IO Coherency Good knowledge of SoC architecture having Multicore/Multiprocessor with SMP/heterogenous cores Knowledge of Operating systems/RTOS/Linux kernel internals, multithreading, scheduling policies/locking mechanism, Virtual memory/MMU/paging etc Understanding of memory management, weakly ordered memory model/pipelining of memory systems/memory barriers In-depth understanding of software build toolchains comprising of compilers, Makefiles, linker/scatter files Compiler/Linker: Proficient in using compilers and linkers such as GCC, CLANG, RVDS, LLVM, Experience in optimizing code and resolving linker issues to ensure efficient and error free builds Makefiles: Strong understanding of the makefile syntax and usage. Ability to create, modify and maintain Makefiles to automate the build process and manage dependencies effectively Experience in using JTAG interfaces and tools for debugging HW Scripting languages such as Python, shell scripting etc. Desired Skills Exposure to SoC architecture paradigms interconnects, power management, emulation(pre-Si) environment Exposure to working on emulation/pre-si environment is added advantage Experience working with boot code for ARM processors Software development for silicon enablement, silicon validation Board Bring-up/Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs Exposure to build automation: Experience with build automations tools such as Jenkins and experience in creating automated build pipelines to stream line the development process Exposure to Regression testing: Understanding of the regression testing methodologies and tools. Ability to design, implement and execute comprehensive regression test suites to ensure software quality and stability Source code management: Proficient in source code management tools such as Perforce, Git, SVN. Experience in branching merging and resolving merge conflicts Code Reviews: Ability to conduct thorough and constructive code reviews to maintain code quality, ensure best practices and identify the areas of improvements

About The Role : Defines, develops, and performs functional validation for integrated SoCs, focusing on validation of IP integration, interaction between IPs, and systemlevel features. Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met. Reviews proposed design changes to assess impact on validation plans, tasks, and timelines. Develops SoC validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis. Performs silicon debug to identify root causes and resolves all functional and triage failures for SoC issues. Tests interactions between various SoC features using validation infrastructure. Develops postsilicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing. Publishes SoC validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams. Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for SoC interfaces and to meet desired product specifications. Develops content to create or increase specific IP interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom OS builds). Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, FPGAs) to ensure silicon readiness. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.tech/M.Tech with 3 to 6 yrs of experience in pre and post silicon validation. Hands on in python script development. Experience in SOC debug tools enabling. Preferred Qualifications: Understanding of SOC architecture will be a plus. Behavioral skills, communication skills. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Working Model This role will require an on-site presence.

Position: Design Verification Manager Experience: 12+ yrs (IC + People Management) Qualification: B.Tech / B.E or M.Tech / ME in EEE/ECE Job Location: Bangalore Job Type & Shift: Permanent & Day Shift Major Responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Skills & Qualifications Required: 12+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience with ARM/RISCV Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills Kindly Note: We are looking for candidates who can join 15 to 30 days notice max. For more details please feel free to reach out Karthik @ 7658983115 or You may DM your updated profile to: karthik.b@creenosolutions.com

Position: Android Test Engineers (SDET) Experience: 3 to 6 yrs Role: Individual Contributor Qualification: B.Tech / B.E / M.Tech / M.E Job Type: Permanent & Work From Office Job Location: Bangalore The charter of the Android Test team is to ensure that the end-product qualifies Google requirements. The team is looking for a candidate who has strong understating of Android framework, test methodologies, troubleshooting/analyzing failures and running Continuous Integration, Kernel, and other functional & compliance test cases. The position involves understanding of SOC Architecture, triaging test failures and routing to the right tech area. Good Experience with test methodologies, writing test plans, creating test cases, and debugging Candidate would also require contributing to the test automation on need basis Mandatory: Excellent triage and system level debugging skills. The candidate is expected to be self-driven to quickly get up to speed on various aspects of android testing & flexible to take-up tasks as per the project needs. Experience with coding languages: C, C++, Java or Python Interested candidates with the matched skills and experience please share your updated profile to: karthik.b@creenosolutions.com or may reach out Karthik @ 7658983115 for more details. Kindly Note: We are looking for candidates who can join 15 to 30 days notice max.