Lead Verification Engineer

Role & responsibilities

• Define verification strategies and develop verification plans for complex SoC components and subsystems.
• Lead the creation of testbenches and verification environments using SystemVerilog and UVM.
• Drive functional, assertion-based, and coverage-driven verification methodologies.
• Collaborate with RTL, architecture, and firmware teams to identify corner cases and critical design scenarios.
• Debug and root-cause functional issues using simulation tools and waveform analysis.
• Review and optimize test plan coverage metrics and drive coverage closure.
• Automate and manage regression suites and analyze simulation results.
• Guide junior engineers and perform code reviews.
• Coordinate with DFT and implementation teams for seamless integration and verification closure.
• Maintain high-quality documentation for test plans, strategies, and coverage reports.
• Perform static timing analysis (STA) and logic equivalence checks (LEC)

Preferred candidate profile

• Define verification strategies and develop verification plans for complex SoC components and subsystems.
• Lead the creation of testbenches and verification environments using SystemVerilog and UVM.
• Drive functional, assertion-based, and coverage-driven verification methodologies.
• Collaborate with RTL, architecture, and firmware teams to identify corner cases and critical design scenarios.
• Debug and root-cause functional issues using simulation tools and waveform analysis.
• Review and optimize test plan coverage metrics and drive coverage closure.
• Automate and manage regression suites and analyze simulation results.
• Guide junior engineers and perform code reviews.
• Coordinate with DFT and implementation teams for seamless integration and verification closure.
• Maintain high-quality documentation for test plans, strategies, and coverage reports.
• Perform static timing analysis (STA) and logic equivalence checks (LEC)

Preferred Skills (Nice to Have)

• Experience with low power verification (UPF/CPF).
• Exposure to formal verification tools and techniques.
• Knowledge of AMBA (AXI/AHB/APB) and other common bus protocols.
• Familiarity with FPGA prototyping, silicon bring-up, or post-silicon validation.