5 Cadence Xcelium Jobs

The ideal candidate for this role should hold a Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field or possess equivalent practical experience. Additionally, you should have at least 5 years of experience working with ML/AI frameworks and libraries such as TensorFlow, PyTorch, and scikit-learn. It is essential to have a background in hardware description languages like Verilog, SystemVerilog, and VHDL, along with experience in applying ML/AI techniques. Preferred qualifications include hands-on experience with ML/AI applications in hardware design, verification, and Low Power, such as formal verification with ML and coverage closure with ML. Familiarity with verification methodologies like UVM and OVM is highly advantageous. Proficiency in data preprocessing, feature engineering, hardware architecture, microarchitecture, and simulation tools like Synopsys VCS, Cadence Xcelium, and Mentor Questa is preferred. Excellent programming skills in Python or C++ are also desirable. As a member of our team, you will be part of a group that continually pushes boundaries by developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a crucial role in innovating products that are adored by millions worldwide, shaping the next generation of hardware experiences to deliver unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team leverages the best of Google AI, Software, and Hardware to create incredibly helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include researching, designing, and implementing ML/AI algorithms and techniques for various verification tasks, such as test case generation, coverage analysis, bug prediction, and performance optimization. You will be tasked with developing and maintaining tools and scripts for data collection, preprocessing, model training, and evaluation. Additionally, you will analyze large datasets of simulation results, logs, and other verification data to identify patterns and trends, building and training ML models for various verification applications, and evaluating model performance to enhance accuracy and efficiency. Furthermore, you will participate in verification planning, developing test plans that integrate ML/AI-driven techniques, executing verification tests, and analyzing results to pinpoint bugs and coverage gaps. You will also be responsible for developing and maintaining verification tools and scripts to automate verification tasks effectively.,

Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years of hands-on DV experience in SystemVerilog/UVM, you will be responsible for owning and driving the verification of a block/subsystem or a SOC. An ideal candidate should have a proven track record of leading a team of engineers and possess extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Proficiency in Tesplan and Testbench development, execution of test plans using high-quality constrained random UVM tests to achieve coverage goals on time, and adeptness in debugging and exposure to all aspects of verification flow including Gatesims are essential. The candidate must have extensive experience in the verification of technologies such as PCI Express or UCIe, CXL or NVMe, AXI, ACE or CHI, Ethernet, RoCE or RDMA, DDR or LPDDR or HBM, ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages, and Power Aware Simulations using UPF. Experience in using EDA tools like VCS, Verdi, Cadence Xcelium, Simvision, Jasper, and revision control systems such as Git, Perforce, Clearcase is required. Experience in SVA and formal verification is desirable, and knowledge of script development using Python, Perl, or TCL is an added advantage. The position is available in various locations including Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, and Pune. The ideal candidate must have a minimum of 7 years of YoE. Key Responsibilities: - Define product requirements and implement VLSI and hardware devices - Continuously upgrade and update design tools and frameworks - Analyze and select the right components and hardware elements for product engineering - Conduct cost-benefit analysis to choose the best design - Develop architectural designs for new and existing products - Implement derived solutions and troubleshoot critical problems - Evangelize architecture to project and customer teams to achieve the final solution - Monitor product solution and make continuous improvements - Understand market-driven business needs and technology trends to define architecture requirements and strategy - Develop Proof of Concepts (POCs) to demonstrate product feasibility - Provide solutioning for RFPs from clients and ensure overall product design assurance - Collaborate with sales, development, and consulting teams to reconcile solutions to architecture - Provide technical leadership in designing custom solutions using modern technology - Validate solutions from technology, cost structure, and customer differentiation perspectives - Identify and resolve problem areas in architectural design and solutions - Monitor industry and application trends and provide strategic input during product deployment - Support delivery team in product deployment and issue resolution - Develop product validation and performance testing plan in alignment with business requirements - Maintain product roadmap and provide inputs for product upgrades based on market needs - Build competencies and branding through necessary trainings, certifications, and Thought leadership content development - Mentor developers, designers, and junior architects for career enhancement - Contribute to the architecture practice by conducting selection interviews Performance Parameters: - Product design, engineering, and implementation: Measure based on CSAT, quality of design/architecture, FTR, delivery as per cost, quality, and timeline, POC review and standards - Capability development: Measure based on % of trainings and certifications completed, mentorship of technical teams, and development of Thought leadership content Wipro is dedicated to reinventing your world by building a modern, end-to-end digital transformation partner with ambitious goals. The company is looking for individuals who are inspired by reinvention and are committed to constant evolution in their careers and skills. Join Wipro to realize your ambitions and be part of a purpose-driven business that empowers you to design your own reinvention. Applications from people with disabilities are explicitly welcome.,

You are an AMS Verification engineer with a B.Tech/M.Tech degree and 5-11 years of industry experience in analog/mixed signal behavioral modeling. Your responsibilities include full chip verification at various levels using SV RNM or Custom UDNs. You should have a good understanding of analog design concepts and mixed signal design architectures, working with products integrating various Analog/Mixed-Signal building blocks. Your experience should cover verification plan development, UVM verification environment development/debug, and verification of complex mixed signal products at different levels. Familiarity with Analog/Mixed-Signal/RF design architectures, debug experience with schematic capture tools, and co-simulations with analog model/transistor level and digital RTL/Gate+SDFs are essential. You should also have experience in circuit simulations with Spice/Fast Spice simulators and digital simulators like Cadence Xcelium/DMSO/Synopsys VCS. Developing self-checking testcases, tracking verification metrics, regression management, and using tools such as Cadence vManager for Metric Driven Verification are part of your role. You must be quick to adopt new technologies, possess good problem-solving skills, and collaborate effectively with team members from various disciplines. Your role is based in Bangalore, and you should be self-motivated, enthusiastic, and able to close the verification of analog designs using industry standard metrics within a notice period of 0-30 days.,

Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer Partial Ability to drive MSV project independently Drive enhancements in known methodologies You are best equipped for this task if you have: Bachelors with 5+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently Contact: [HIDDEN TEXT] #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profile Experienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools (Xcelium/Simvision), netlist & gate-level simulations, coverage closure, debugging, and scripting.