13 Cadence Xcelium Jobs

Job Description: Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients. Key Responsibilities Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans. Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology) . Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs. Develop verification components, including drivers, monitors, s...

4 to 10 years experience in SoC/Subsystem Design Verification SystemVerilog and UVM Testbench creation experience is a must Own and drive Defining/Implementation of test plans Debugging complex issues Completion of coverage including gate-level simulations Experience in writing SVA (SystemVerilog Assertions) is a must Protocol Expertise (Deep knowledge and hands-on expertise) on one or more of the following PCIe, UCIe, CXL, or NVMe AXI, ACE or CHI Ethernet DDR, LPDDR or HBM Should have worked on verification of at least three full-chip/subsystem DV projects EDA tools Synopsys VCS/ Cadence Xcelium and Verdi debugger Experience of Power Aware Simulations using UPF is desirable (not a must) Exp...

As an ASIC Verification Engineer, you will collaborate with design and verification engineers to develop and execute robust verification strategies. You will be responsible for creating and maintaining testbenches and test cases aligned with test plans and design specifications. Additionally, you will develop, enhance, and maintain UVM-based verification frameworks to ensure the reliability of ASIC design. Your role will involve delivering automated regression suites to reduce risk and contribute to unit-level and system-level verification deliverables for complete test coverage. Furthermore, you will design and maintain a verification environment for testing RTL implementations against refe...

Job Requirements Design Verification professional with a proven track record in leading DV projects for complex SoC/ASIC/FPGA designs. This role will be working closely with world class engineering teams to ensure design quality, performance, and verification closure on cutting-edge hardware products. Key Responsibilities Lead the DV team in planning, developing, and executing verification strategies for SoC/ASIC designs. Collaborate with architects, RTL designers, and validation engineers to define verification requirements and methodologies. Develop and maintain verification environments using UVM/SystemVerilog. Drive code reviews, functional coverage analysis, and regression tracking to a...

Role & responsibilities Define verification strategies and develop verification plans for complex SoC components and subsystems. Lead the creation of testbenches and verification environments using SystemVerilog and UVM. Drive functional, assertion-based, and coverage-driven verification methodologies. Collaborate with RTL, architecture, and firmware teams to identify corner cases and critical design scenarios. Debug and root-cause functional issues using simulation tools and waveform analysis. Review and optimize test plan coverage metrics and drive coverage closure. Automate and manage regression suites and analyze simulation results. Guide junior engineers and perform code reviews. Coordi...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...

Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort coming up with alternative verification plans- Full Self-motivated to drive new scope expansion proposals mapping to business value Mentoring junior engineers in creating prob...

Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS Job Description In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -Partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort coming up with alternative verification plans- Full Self-motivated to drive new scope expansion proposals mapping to business value Mentoring junior engineers in creati...

The ideal candidate for this role should hold a Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field or possess equivalent practical experience. Additionally, you should have at least 5 years of experience working with ML/AI frameworks and libraries such as TensorFlow, PyTorch, and scikit-learn. It is essential to have a background in hardware description languages like Verilog, SystemVerilog, and VHDL, along with experience in applying ML/AI techniques. Preferred qualifications include hands-on experience with ML/AI applications in hardware design, verification, and Low Power, such as formal verification with ML and coverage closure with ML...

Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years ...

You are an AMS Verification engineer with a B.Tech/M.Tech degree and 5-11 years of industry experience in analog/mixed signal behavioral modeling. Your responsibilities include full chip verification at various levels using SV RNM or Custom UDNs. You should have a good understanding of analog design concepts and mixed signal design architectures, working with products integrating various Analog/Mixed-Signal building blocks. Your experience should cover verification plan development, UVM verification environment development/debug, and verification of complex mixed signal products at different levels. Familiarity with Analog/Mixed-Signal/RF design architectures, debug experience with schematic...

Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS o...

We are hiring DV Contract Engineers with 10+ years of experience in UVM-based testbenches, netlist/gate-level simulations, and datapath blocks. Strong expertise in Cadence tools (Xcelium/Simvision) and scripting (Python/Shell) required. Required Candidate profile Experienced DV engineer with 10+ years in verification, UVM testbench, Cadence tools (Xcelium/Simvision), netlist & gate-level simulations, coverage closure, debugging, and scripting.