11 Synopsys Vcs Jobs

You have an exciting opportunity with Tessolve Semiconductor in Bangalore for the roles of RTL Design Engineer and Design Verification Engineer. For the position of RTL ASIC Engineer, you should have at least 7 years of work experience in ASIC/IP Design with expertise in Logic design and RTL design. Your responsibilities will involve IP design and integration, along with proficiency in tools such as Lint and CDC for ASIC development. Knowledge of Synthesis and understanding of timing concepts would be advantageous. Additionally, familiarity with AMBA protocols like AXI, AHB, APB, and SoC clocking/reset architecture is preferred. As a Design Verification Engineer, you are required to have 5 to 20 years of experience. You should be well-versed in IP verification using SV/UVM, SOC Verification using C/SV, and Third Party VIP Integration. Your expertise in Interconnect Protocols such as AHB, AXI, APB, SOC Interfaces like GPIO, SPI, I2C, UART, High-Speed Serial Interfaces including PCIe Gen 3/4, USB, MIPI, and Memory Interfaces like DDR or HBM I/O will be crucial. Proficiency in Coverage Closure (Code, Functional, Toggle) and tools like Synopsys VCS or Cadence Incsive is essential. Experience in Technical Documentation, Foundry Porting, and Technology Library Conversion related to Verification will be advantageous. If you meet the requirements and are interested in these positions, please share your updated CV with Gayatri Kushe at gayatri.kushe@tessolve.com or contact at 6361542656. Thank you for considering this opportunity with Tessolve Semiconductor.,

Role : RTL Synthesis Engineer (Vivado Backend / RTL Synthesis ,Hyderabad) Work Location (Client): Hyderabad Work Mode or timing : Work From Office / Normal Working hours Qualification : MS or equivalent work experience in Electrical Engineering or similar technology area Experience Level : 4+ years Job Description : An experienced application engineer to focus on FPGA & ACAP Compilation flows, design closure ease-of-use, tools specification, validation, documentation, and key customers support Responsibilities Contribute to triaging reported issues in several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices, with emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family. Develop and deliver training materials on new features and methodologies. Stay current with and propose the internal use of industry approaches, algorithms, and practices.

The ideal candidate for this role should hold a Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field or possess equivalent practical experience. Additionally, you should have at least 5 years of experience working with ML/AI frameworks and libraries such as TensorFlow, PyTorch, and scikit-learn. It is essential to have a background in hardware description languages like Verilog, SystemVerilog, and VHDL, along with experience in applying ML/AI techniques. Preferred qualifications include hands-on experience with ML/AI applications in hardware design, verification, and Low Power, such as formal verification with ML and coverage closure with ML. Familiarity with verification methodologies like UVM and OVM is highly advantageous. Proficiency in data preprocessing, feature engineering, hardware architecture, microarchitecture, and simulation tools like Synopsys VCS, Cadence Xcelium, and Mentor Questa is preferred. Excellent programming skills in Python or C++ are also desirable. As a member of our team, you will be part of a group that continually pushes boundaries by developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a crucial role in innovating products that are adored by millions worldwide, shaping the next generation of hardware experiences to deliver unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team leverages the best of Google AI, Software, and Hardware to create incredibly helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include researching, designing, and implementing ML/AI algorithms and techniques for various verification tasks, such as test case generation, coverage analysis, bug prediction, and performance optimization. You will be tasked with developing and maintaining tools and scripts for data collection, preprocessing, model training, and evaluation. Additionally, you will analyze large datasets of simulation results, logs, and other verification data to identify patterns and trends, building and training ML models for various verification applications, and evaluating model performance to enhance accuracy and efficiency. Furthermore, you will participate in verification planning, developing test plans that integrate ML/AI-driven techniques, executing verification tests, and analyzing results to pinpoint bugs and coverage gaps. You will also be responsible for developing and maintaining verification tools and scripts to automate verification tasks effectively.,

You are an AMS Verification engineer with a B.Tech/M.Tech degree and 5-11 years of industry experience in analog/mixed signal behavioral modeling. Your responsibilities include full chip verification at various levels using SV RNM or Custom UDNs. You should have a good understanding of analog design concepts and mixed signal design architectures, working with products integrating various Analog/Mixed-Signal building blocks. Your experience should cover verification plan development, UVM verification environment development/debug, and verification of complex mixed signal products at different levels. Familiarity with Analog/Mixed-Signal/RF design architectures, debug experience with schematic capture tools, and co-simulations with analog model/transistor level and digital RTL/Gate+SDFs are essential. You should also have experience in circuit simulations with Spice/Fast Spice simulators and digital simulators like Cadence Xcelium/DMSO/Synopsys VCS. Developing self-checking testcases, tracking verification metrics, regression management, and using tools such as Cadence vManager for Metric Driven Verification are part of your role. You must be quick to adopt new technologies, possess good problem-solving skills, and collaborate effectively with team members from various disciplines. Your role is based in Bangalore, and you should be self-motivated, enthusiastic, and able to close the verification of analog designs using industry standard metrics within a notice period of 0-30 days.,

We HCL are seeking a highly motivated RTL Design Engineer with 7-12 years of experience to join our growing team. You will play a vital role in the design and development of complex digital logic for next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in RTL design methodologies and verification. Responsibilities: Design and develop RTL code for digital logic blocks and modules using Verilog or VHDL Perform comprehensive functional verification using industry-standard methodologies (e.g., UVM) Conduct static timing analysis (STA) and participate in timing closure activities Integrate designed modules into larger subsystems and ensure seamless functionality Collaborate effectively with design, verification, and synthesis teams throughout the development cycle Write clear, concise, and well-documented RTL code adhering to coding standards Stay current with advancements in RTL design tools and methodologies Qualifications: Bachelor&aposs degree in Electrical Engineering, Computer Engineering, or a related field (Master&aposs degree a plus) 7-12 years of solid experience in RTL design for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to design and verify high-performance and efficient digital circuits Expertise in Verilog or VHDL with a strong understanding of coding styles and best practices Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) Familiarity with SDC (Standard Delay Constraint) format for timing analysis Excellent problem-solving skills and a meticulous attention to detail Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement Show more Show less

You will be joining Eximietas as a Senior Design Verification Engineer/Lead in Bengaluru with 5-15 years of experience. Your primary responsibility will be to lead the SoC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. This includes developing and implementing comprehensive verification strategies for high-speed and low-speed peripherals such as I2C, SPI, UART, GPIO, QSPI, as well as high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, HBM. You will be conducting Gate-level simulations and power-aware verification using tools like Xprop and UPF. Collaboration with cross-functional teams, including architects, designers, and pre/post-silicon verification teams, will be crucial to ensure alignment and seamless integration of verification efforts. Your role will involve analyzing and implementing System Verilog assertions and functional coverage to ensure thorough verification of design functionality. Mentorship and technical guidance to junior verification engineers will be part of your responsibilities to elevate team performance. Leading and managing a dynamic team of verification engineers, fostering a collaborative and innovative work environment will be essential. You will also ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Your dedication, work ethic, and commitment to meeting project goals and deadlines will be vital. Upholding quality standards and implementing best test practices to contribute to continuous improvements in verification methodologies will also be expected. You will work with verification tools from Synopsys and Cadence, including VCS and Xsim, and integrate third-party VIPs (Verification IP) to enhance verification coverage. To qualify for this role, you should have 5+ years of hands-on experience in SoC Design Verification and expertise in verification of high-speed SoCs and various protocols. Proficiency in System Verilog for verification, gate-level simulations, and power-aware verification using Xprop and UPF are necessary. Strong hands-on experience with VCS and Xsim from Synopsys and Cadence, mentorship experience, and demonstrated ability to work with cross-functional teams are also required. A strong understanding of verification methodologies and the ability to contribute to their continuous improvement are essential.,

We are seeking a highly skilled and experienced Lead Verification Engineer with expertise in USB/LPDDR and a strong knowledge of Cadence VIP. The ideal candidate will have a deep understanding of low-power design and verification techniques. Responsibilities: Develop and execute comprehensive verification strategies for USB/LPDDR subsystem designs, considering low-power design requirements. Collaborate with cross-functional teams to define verification goals and ensure alignment with project objectives. Design and implement reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based . Leverage Cadence VIP and other verification IPs to accelerate the verification process. Low-Power Design VerificationApply expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, including power states, power domains, and power-aware verification methodologies. : Extensive experience (8+ years) in verification. Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). Proficiency in low-power design techniques and power-aware verification methodologies. Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Job Location: Bengaluru (BLR) and Hyderabad (HYD) Experience: 7 to 20 years : We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of ARM Micro Architecture to join our team. In this role, you will play a key role in the development of complex digital designs and contribute to the success of our cutting-edge projects. The ideal candidate will have a proven track record in RTL design and a deep understanding of ARM Micro Architecture. Key Responsibilities: Collaborate with cross-functional teams to define and develop RTL designs for advanced microprocessor-based projects. Design, implement, and verify digital logic blocks and modules in accordance with project specifications and quality standards. Utilize your expertise in ARM Micro Architecture to optimize and enhance design efficiency. Perform RTL simulations and conduct thorough functional and timing analysis. Identify and resolve design issues, ensuring the delivery of high-quality RTL designs. Stay up-to-date with industry trends and emerging technologies to continually improve design methodologies. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience as an RTL Design Engineer with 7 to 20 years of relevant work experience. Strong knowledge of ARM Micro Architecture and its application in RTL design. Proficiency in RTL design tools and methodologies. Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS). Excellent problem-solving skills and attention to detail. Effective communication and collaboration skills. Ability to work effectively in a dynamic and fast-paced environment. If you are a highly motivated and experienced RTL Design Engineer with a passion for innovation and a strong background in ARM Micro Architecture, we encourage you to apply for this exciting opportunity. Join our team and contribute to the development of cutting-edge technology solutions. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore IndiaHyderabad

We are seeking an experienced and dedicated Design and Verification Trainer to provide guidance and support to budding engineers in the areas of RTL design, functional verification, and VLSI concepts. As a Trainer, you will draw upon your practical experience in front-end design and verification methodologies to effectively convey technical knowledge in an organized, engaging, and articulate manner. Your role will require a strong command over hardware description languages such as Verilog and SystemVerilog, along with a deep understanding of verification methodologies including UVM and SystemVerilog Assertions. Proficiency in simulation and debugging tools like Synopsys VCS, VERDI, and Spyglass is essential for this position. Additionally, expertise in scripting, analytical thinking, and problem-solving skills will be advantageous in delivering high-quality training sessions. The ideal candidate should hold a Master's degree in Electronics or VLSI Design, although equivalent qualifications will also be considered. Prior experience in curriculum development, instructional design, and teaching is highly desirable. Effective communication and presentation skills are crucial to effectively convey complex concepts to learners. Previous exposure to the VLSI design or semiconductor industry, as well as proficiency in Design Thinking, will be beneficial in this role. If you are passionate about sharing your knowledge and expertise in design and verification, and possess the requisite qualifications and skills, we invite you to join our team as a Design and Verification Trainer.,

SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Description: The verification team is looking for a Senior Design Verification Engineer to contribute on the verification of Network on Chip IPs, Subsystems having adequate knowledgeble on the boot flow. The individual will help architect, develop and use simulation and/or formal based verification environments, at block, subystem , Fulchip level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs. Responsibilities: Plan verification of complex digital design blocks by fully understanding the architecture and design specification Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics General requirements: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification Strong understanding of different phases of ASIC and/or full custom chip development is required Experience in block level NOC (Network on Chip) verification is a plus Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus Special Requirements : Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog; Test plan development and test writing; Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip; Functional coverage writing, coverage collection and analysis, coverage closure; Writing System Verilog assertions and assertion based verification; and, Running regressions, automation using scripting languages such as PERL and verification closure Education Requirements: Masters / B.Tech / M.Tech Years of Experience : 5+ Years #LI-SG

Job Details: : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or schoolwork/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-8 years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5-7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of related work experience. Minimum Qualifications- 4+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience. 4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools. 4+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. 4+ years of experience in OVM/UVM for developing verification test benches and constrained random verification. Preferred Qualifications- Experience with PCIe, Power Management, Ethernet, Network packet processing. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *