Responsibilities: * Collaborate with marketing team on lead generation strategies * Meet monthly sales targets * Manage international client relationships via phone/email * Close US & global deals through inside sales techniques .
Responsibilities: * Design and optimization of SRAMs, ROMs, CAMs, sense amps, bitcells, decoders Development of analog/mixed-signal IPs op-amps, comparators, LDOs, DAC/ADC Schematic design, simulation , layout collaboration, and sign-off Provident fund Health insurance Food allowance
Role & responsibilities Lead end-to-end development of Edge AI models: (Human activity recognition, fall detection, predictive maintenance, anomaly detection, etc.) Architect lightweight models (e.g., TinyML, TFLite Micro) for microcontrollers and IoT devices. Collaborate with hardware, embedded, and firmware teams for edge deployment. Use techniques like: (Model quantization, pruning, knowledge distillation, ONNX conversion) Signal preprocessing (FFT, time-domain, sensor fusion) Drive data collection strategies for real-world edge use cases. Own model performance metrics: (Accuracy, latency, power consumption, memory footprint) Mentor a team of ML engineers and scientists; review code and model pipelines. Stay up to date with trends in TinyML, edge computing, and AI acceleration. Preferred candidate profile Lead end-to-end development of Edge AI models: (Human activity recognition, fall detection, predictive maintenance, anomaly detection, etc.) Architect lightweight models (e.g., TinyML, TFLite Micro) for microcontrollers and IoT devices. Collaborate with hardware, embedded, and firmware teams for edge deployment. Use techniques like: (Model quantization, pruning, knowledge distillation, ONNX conversion) Signal preprocessing (FFT, time-domain, sensor fusion) Drive data collection strategies for real-world edge use cases. Own model performance metrics: (Accuracy, latency, power consumption, memory footprint) Mentor a team of ML engineers and scientists; review code and model pipelines. Stay up to date with trends in TinyML, edge computing, and AI acceleration.
Role & responsibilities • Lead design and development of the AI/ML compiler toolchain for Ambients ultra-low power AI chips. Build and optimize compiler backends, IR transformations, and runtime systems for AI workloads. Drive model conversion pipelines (TF, TFLite, PyTorch, ONNX Ambient compiler stack). Implement graph-level and operator-level optimizations (fusion, scheduling, memory reuse). Collaborate with hardware and data science teams to co-design hardware-aware compiler strategies. Develop tools for quantization, pruning, mixed precision, and efficient memory allocation. Ensure compiler generates binaries with predictable latency, power, and memory footprint. Define performance metrics and benchmarking strategies for compiler outputs. Mentor a team of compiler and software engineers; review design, code, and optimization flows. Stay up to date with MLIR, LLVM, XLA and latest AI compiler trends. Preferred candidate profile Bachelor’s/Master’s in CSE, ECE, EEE, or related. 7+ years of experience in compiler development, with at least 3+ years in ML compilers/AI acceleration. Strong expertise in compiler internals: parsing, IR design, optimization passes, code generation. Proficiency in C/C++, Python, LLVM/MLIR, ONNX Runtime. Solid understanding of neural network architectures, graph optimization, and hardware acceleration. Familiarity with DSPs, GPUs, and AI accelerators; knowledge of edge hardware (ARM Cortex-M, RISC-V) desirable. Experience in runtime systems, scheduling, and memory management for constrained devices. Excellent leadership, problem-solving, and cross-functional collaboration skills.
Role & responsibilities Define verification strategies and develop verification plans for complex SoC components and subsystems. Lead the creation of testbenches and verification environments using SystemVerilog and UVM. Drive functional, assertion-based, and coverage-driven verification methodologies. Collaborate with RTL, architecture, and firmware teams to identify corner cases and critical design scenarios. Debug and root-cause functional issues using simulation tools and waveform analysis. Review and optimize test plan coverage metrics and drive coverage closure. Automate and manage regression suites and analyze simulation results. Guide junior engineers and perform code reviews. Coordinate with DFT and implementation teams for seamless integration and verification closure. Maintain high-quality documentation for test plans, strategies, and coverage reports. Perform static timing analysis (STA) and logic equivalence checks (LEC) Preferred candidate profile Define verification strategies and develop verification plans for complex SoC components and subsystems. Lead the creation of testbenches and verification environments using SystemVerilog and UVM. Drive functional, assertion-based, and coverage-driven verification methodologies. Collaborate with RTL, architecture, and firmware teams to identify corner cases and critical design scenarios. Debug and root-cause functional issues using simulation tools and waveform analysis. Review and optimize test plan coverage metrics and drive coverage closure. Automate and manage regression suites and analyze simulation results. Guide junior engineers and perform code reviews. Coordinate with DFT and implementation teams for seamless integration and verification closure. Maintain high-quality documentation for test plans, strategies, and coverage reports. Perform static timing analysis (STA) and logic equivalence checks (LEC) Preferred Skills (Nice to Have) Experience with low power verification (UPF/CPF). Exposure to formal verification tools and techniques. Knowledge of AMBA (AXI/AHB/APB) and other common bus protocols. Familiarity with FPGA prototyping, silicon bring-up, or post-silicon validation.
Responsibilities:- Develop and implement Register Transfer Level (RTL) design for digital circuits using Verilog/SystemVerilog/VHDL. Architect and design key functional blocks, ensuring efficient and optimised hardware implementation. Define microarchitecture based on architecture specifications and requirements. Collaborate with system architects and design teams to refine features and performance trade-offs. Work closely with verification teams to ensure functional correctness through simulation, formal verification, and debugging. Support post-silicon debugging and bring-up activities. Performance Optimisation & Power Efficiency. Optimise RTL for power, performance, and area (PPA) trade-offs. Perform timing closure, power analysis, and clock domain crossings (CDC) checks. Collaborate with the physical design team to ensure synthesis, timing closure, and DFT (Design for Testability) requirements. Ensure the RTL is synthesis-friendly and meets target constraints. Work with cross-functional teams (architecture, verification, physical design, software, validation). Document design specifications, architecture, and implementation details Requirement:- Strong understanding of digital design fundamentals, VLSI, and SoC architecture. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proficiency in hardware description languages (HDL) like Verilog or VHDL. Experience with CAD tools and EDA software. Strong analytical and problem-solving skills. Ability to work effectively in a team environment and independently. Good communication skills and a proactive attitude
You will play a crucial role in using test automation frameworks and designing and developing test automation scripts. Using test automation guidelines and managing the testing process. finding bugs in the software through testing. Food allowance Health insurance Provident fund
Role & responsibilities 1. Demand Generation & Business Growth Identify and engage potential customers and design partners across industrial, consumer, and smart device segments. Drive design-in and design-win opportunities by understanding customer needs and mapping them to Ambients technology offerings. Collaborate with channel partners sales teams to ensure strong funnel growth, lead qualification, and conversion metrics. 2. Technical Program Management Act as the primary interface between Channel partner of Ambient Scientific, and end customers on all technical engagements. Support customer evaluations, proof-of-concept builds, and prototyping efforts with Ambients engineering teams. Coordinate technical discussions, track project milestones, and ensure timely issue resolution. 3. Channel Enablement & Collaboration Conduct product trainings, workshops, and technical sessions for channel partner sales team and FAE teams. Ensure updated marketing collateral, datasheets, and demo kits are available and effectively used in customer engagements. Work closely with Ambient Scientifics marketing and technical teams to align local campaigns, events, and media activities. 4. Forecasting & Reporting Own the business metrics for the Ambient Scientific product line — including revenue targets, funnel health, and design win tracking. Provide regular business reviews and market feedback to both DTDS and Ambient Scientific management teams. Maintain accurate sales forecasts, inventory planning, and opportunity reports. Preferred candidate profile Experience with AI at the edge , sensor fusion, or ultra-low-power compute devices. Exposure to global semiconductor partners or startups with advanced technologies. Familiarity with Indian OEM and ODM ecosystem in wearables, healthcare, or industrial IoT domains.