Technical Lead ASIC Verification Engineer

Role Overview: You will be joining AMD as an ASIC Verification Engineer. Your main responsibility will be to drive strategies and lead successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs. Key Responsibilities: - Lead a team and collaborate with cross-functional teams to plan inter-locks with dependent teams, pre-empt risks, and have mitigation plans in place. - Develop UVM/OVM and/or Verilog, System Verilog test benches and utilize simulation tools/debug environments like Synopsys VCS, Cadence IES for verifying high-performance IPs and/or SOC designs. - Implement state-of-the-art verification techniques including assertion and metric-driven verification. Establish the verification methodology, tools, and infrastructure for high-performance IP and/or VLSI designs. - Utilize FPGA programming and software expertise, and work with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan / VC Formal). - Conduct gate-level simulation, power-aware verification, reset verification, and contention checking. Previous experience with silicon debug at the tester and board level is beneficial. Qualification Required: - Must have 15+ years of experience in technically leading a team and working with cross-functional teams for verification of high-performance IPs and/or SOC designs. - Strong proficiency in development of UVM/OVM and/or Verilog, System Verilog test benches, and usage of simulation tools/debug environments. - Bachelor's or Master's degree in computer engineering or Electrical Engineering. - Prior experience with silicon debug at the tester and board level is a plus. (Note: The additional details about the company benefits have been omitted as they were not explicitly mentioned in the provided job description.),