13 Silicon Debug Jobs

The Wide VIN Buck product line focuses on developing switching controllers for the industrial, automotive, and enterprise markets with a voltage of over 35V. The team in India is expanding its workforce with a clear mandate to drive and accelerate the execution of the product and technology roadmap within this product line. The team will have complete ownership of product development from the initial definition stage to the final market release. We are currently seeking Lead Analog Designers with a minimum of 5+ years of industry experience in switching converters. This role requires a hands-on approach to technical leadership as an individual contributor. The ideal candidate should have prior experience in successfully taking multiple designs to tape out and overseeing silicon testing in the lab, as this experience will enable the lead engineer to seamlessly integrate into the role. Key Responsibilities: - Take the lead in the design function for projects, including hands-on design of critical IP, complete ownership of the full chip top level, and responsibility for sign-off for PG in collaboration with layout and DV functions. - Work closely with the Test team both pre- and post-tape out to ensure the best quality and lowest cost of build are achieved. - Collaborate with the Validation team pre- and post-tape out to ensure comprehensive coverage and effective silicon debugging. - Partner with the Product Engineering team to meet all IC qualification requirements and facilitate the release to production. - Engage with Program Managers to uphold project cost and schedule commitments effectively.,

THE ROLE: AECG SSD ASIC is a centralized ASIC design group within AMD s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. PREFERRED EXPERIENCE: Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

You will be responsible for DFX Verification as a DFX Engineer at Eximietas. With 4-10 years of experience, you should have a good background in SoC RTL verification and debug, GLS simulations and debug, Verilog coding, and a solid understanding of JTAG and verification in Test Mode. It would be beneficial to have experience in pattern generation and Silicon debug. The role does not require MBIST/SCAN related experience. The location for this position is Visakhapatnam. If you meet the requirements and are interested in this opportunity, please share your updated resume with us at maruthiprasad.e@eximietas.design.,

Are you seeking an exciting career opportunity at one of the world's leading semiconductor companies Texas Instruments (TI) is inviting applications for the position of Senior Analog Design Engineer. As part of a dedicated team of engineers, you will be involved in developing highly complex mixed signal devices for audio applications, showcasing industry-leading performance. This role offers a unique chance to join an established team that is continuously seeking growth opportunities. You will collaborate with top-tier customers globally and contribute to the development of cutting-edge solutions in consumer electronics, industrial, and automotive markets. As a prospective candidate, you should hold a Bachelor's or Master's Degree in Electrical Engineering. The ideal candidate will possess 4-10 years of relevant experience in the field. In this role, you can look forward to collaborating with industry experts, enhancing your ability to work in a technically challenging, fast-paced environment, and contributing to innovative semiconductor technology. You will have the opportunity to work on cutting-edge analog and power semiconductor processes, interact with various facilities, and gain insights into product development processes. Your responsibilities will include contributing to core-technology development, defining circuit architectures, developing design schematics, and engaging in design verification. You will take ownership of complex analog circuit design activities, collaborate with cross-functional teams, and drive new design methodologies where needed. Preferred qualifications for this role include strong analytical and problem-solving skills, effective communication abilities, and the capacity to work collaboratively in a dynamic environment. Experience in silicon debug, EM and thermal analysis, EMI and EMC aware designs, and signal processing would be advantageous. If you are looking to further your career in analog design engineering and contribute to the development of innovative semiconductor solutions, we encourage you to apply for this exciting opportunity with Texas Instruments (TI).,

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout activities, ensuring designs meet requirements for DFM and reliability, contributing to methodology development, supporting silicon bring-up, and providing technical leadership to junior engineers. To be successful in this role, you should have a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering, along with 8+ years of experience in full-custom memory design. You should possess a solid understanding of CMOS analog/digital circuit design principles, expertise in circuit simulation tools, experience with advanced nodes, and hands-on experience with variation analysis, IR drop, and EM checks. Strong analytical, communication, and leadership skills are essential for this position. Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,

The BSM product line, part of the Motor Drive products group in ASC, is a key focus area for R&D and product development at TI. The team primarily concentrates on Precise Signal, Intelligent Control, and Power transfer. Key challenges involve innovative circuit & architecture techniques for precise control and diagnostics, achieving high power density, high efficiency, medium to high voltage circuit architectures, precise signal chain solutions, intelligent algorithm development, protection circuits for diagnostics and safety, and rugged & robust designs meeting stringent ESD, Latch-up & Emissions spec. Additionally, the team focuses on driving process/technology/package development for cost and performance optimization. The available positions in this group are for working on the Isolation family of products. Applicants should have 4 - 10 years of experience in Analog circuits & architecture design. **Basic Qualifications:** - Bachelor's/Master's Degree in EE - Strong Electrical engineering fundamentals & basic analog building blocks - Experience in design of Analog & Power Management Circuits - Experience in leading full block/chip activity like circuit block spec definition, top-level simulations, driving design verification and design for test - Good mentoring, communication, presentation skills, and teamwork **Preferred Qualifications:** - Experience in defining circuit architecture for PMIC, Signal Chain &/or Analog Circuits - Ability to execute complex analog, power & mixed signal designs from concept to PG - Experience in silicon debug and characterization **Primary Responsibilities:** - Developing circuit architecture for the chip based on datasheet/system specifications - Creating chip schematics and engaging in design and verification - Developing individual block design specification based on full chip circuit architecture - Ownership of design & layout activities including technical mentoring and schedule planning and tracking - Collaborating with cross-functional teams to define & model components, automation - Supporting bench and ATE test with test plan, schematic, and layout verification - Silicon Debug, assisting in characterization and qual support,

Key Responsibilities: Ownership of Scan/ATPG and MBIST flows for complex SoCs Expertise in Synopsys tools , especially SMS (Synopsys Memory Solution) Deep understanding of MBIST architecture and memory repair techniques Hands-on experience with Scan insertion and ATPG for large devices using hierarchical DFT flows Debug and support issues during DFT implementation and silicon bring-up Collaborate closely with RTL, PD, and test engineering teams

You will be part of the BSM product line within the Motor Drive products group at ASC. The BSM products play a crucial role in the R&D and product development efforts at TI, focusing on Precise Signal, Intelligent Control, and Power transfer. Your main tasks will involve addressing the following key challenges in product development: - Implementing innovative circuit & architecture techniques for precise control and diagnostics of drivers, while achieving best-in-class power density. - Designing high efficiency, Medium and high voltage circuit architectures to develop high power transfer solutions. - Creating precise signal chain solutions to ensure accurate control loops. - Developing intelligent Algorithms for integrated motors and solenoids motion control. - Designing protection circuits for smart diagnostics and safety of devices. - Ensuring rugged & robust designs that meet stringent ESD, Latch-up & Emissions spec. - Driving process/technology/package development for cost and performance optimization. In this role, you will be required to have 4 - 10 years of experience in Analog circuits & architecture design. The basic qualifications include a Bachelor's/Master's Degree in EE. You should have a strong foundation in Electrical engineering fundamentals & basic analog building blocks, along with experience in designing Analog & Power Management Circuits. Additionally, experience in leading full block/chip activities like circuit block spec definition, top-level simulations, driving design verification, and design for test will be beneficial. Good mentoring, communication, presentation skills, and teamwork are essential. Preferred qualifications for this role include experience in defining circuit architecture for PMIC, Signal Chain &/or Analog Circuits, the ability to execute complex analog, power & mixed signal designs from concept to PG, and experience in silicon debug and characterization. Your primary responsibilities will involve: - Developing circuit architecture for the chip based on datasheet/system specifications. - Creating chip schematics and engaging in design and verification. - Developing individual block design specifications aligned with the full chip circuit architecture. - Taking ownership of design & layout activities, including technical mentoring, schedule planning, and tracking. - Collaborating with cross-functional teams to define & model components and automation. - Supporting bench and ATE tests with test plans, schematic and layout verification. - Assisting in silicon debug, characterization, and qual support.,

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the worlds most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Principal Systems Debug Lead THE ROLE: Technical leader responsible for System and Silicon Debug of AMD EPYC Server products. The successful candidate will work as part of the post-silicon validation group; facilitating all aspects of debug and resolution for system level failures working with engineering teams across AMD. Candidate will be immersed in challenging work developing & executing debug strategy for optimal debug throughput on current product to meet project milestones at POR quality. The system debug lead will also help in driving improvements to current product and future debug methodology. The candidate should be able to work in a global environment while maintaining a synergetic culture. The Person As a key contributor to the success of AMDs product, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry leading technologies to market. As System Debug Lead you will be responsible for post-Silicon debug in the next generation of AMDs flagship server CPU products. In this role you will facilitate the debug efforts of a program to ensure the maximum debug throughput is achieved. The System debug lead will also help to drive improvements in the current product and future debug methodology working withSystem Validation and Engineering teams and other stakeholders (System Architects, IP design, SoC, FW, SW, manufacturing). Key Responsibilities Ensure issues are solved on time with quality. Lead complex debug efforts for internal Silicon findings to identify root cause and resolution. Manage and track technical issues, risks and priorities. Manage customer and executive communications, including program status, risks and opportunities. Publish debug program indicators to identify major roadblocks and drive changes to improve debug throughput. Evaluate at the end of every program milestone if the open issues are gating to go to the next milestone. Drive improvements to the debug process based on the program learnings. Preferred Skills 15+years or more of experience in validation roles involving debugging OS, FW, Silicon, and HW issues. Understanding of PC industry standard busses and their software stack, such asPCIe, CXL. Strong knowledge of X86 architecture, SoC design, memory, RAS & power management Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, Device Drivers and System BIOS interactions. Excellent communication and coordination skills. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Experience in Technical program management. A thorough understanding of datacenter industry technologies and their software stack. Academic Credentials Bachelors/Masters in Computer Engineering with 15+ years of applicable experience. Location: Bangalore, India Benefits offered are described: AMD benefits at a glance. ,

The Custom product business of Texas Instruments is seeking talented Switching Converter design leads to join a dynamic and innovative team dedicated to delivering cutting-edge technologies for custom mobile electronics. As a Switching Converter design lead, you will play a crucial role in selecting converter architectures for various applications such as Buck, Boost, Buck-Boost, Inverting Buck-boost, and SIMO converters. Your primary focus will be on driving efficiency, transient performance, and IDDQ at high operational frequencies to optimize battery life for handheld electronic devices. Ideal candidates should possess a proven track record in leading switching converter designs, showcasing innovation in performance enhancement, and deep expertise in silicon debugging. The Custom product line at Texas Instruments is at the forefront of delivering industry-leading custom IC system solutions, including display and touch power products, charger power products, camera PMICs, power switches/muxes, LED drivers, and high-speed communication interfaces. By integrating signal chain and power components, our solutions empower TI customers to differentiate their products in the personal electronics sector. This role presents a unique opportunity to be part of a world-class semiconductor team dedicated to innovation and excellence. Key Responsibilities: - Lead Analog IC design projects from concept definition to manufacturing release. - Direct and guide a research or technical design function responsible for developing electronic parts and integrated circuits for various applications. - Assign tasks to team members, provide design guidance, develop schedules, and monitor progress throughout the project lifecycle. - Evaluate project results during design and silicon evaluation phases to ensure technical objectives are met. - Collaborate with physical designers, design verification teams, systems engineers, application engineers, and marketing to prepare product briefs, datasheets, and application notes. - Interface with customers, field sales teams, and field applications teams to understand customer requirements and support product development. - Participate in hiring, developing, and evaluating personnel to ensure organizational efficiency and individual growth. Minimum Requirements: - Bachelor's degree in Electrical Engineering or related field. - 8+ years of experience in analog circuit design and switching converter design. Preferred Qualifications: - Proficiency in switching DCDC regulators design, including multi-phase buck, boost, and buck-boost converters. - Strong understanding of control architectures and device physics applicable to Power IC design. - Expertise in tools such as Spectre, Simplis, Matlab, and AMS. - Experience in system-level understanding, IC system partitioning, and architectural tradeoff analysis. - Ability to work closely with customers and internal cross-functional teams to drive successful product development. Organizational and Team Skills: - Strong project management, time management, and problem-solving abilities. - Excellent communication skills and ability to work effectively in a team environment. - Proven track record of delivering high-quality, bug-free IC designs within tight schedules. - Ability to manage tasks with minimal supervision and collaborate with internal and external stakeholders to achieve business success.,

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Interfacewith design team to ensure DFT design rules andcoveragesare met. Generating high quality manufacturingATPGtest patterns for stuck-at(SAF), transition fault(TDF)modelsthrough the use ofon-chip test compression techniques. MBISTverification(including repair),testpattern generation through Mentor tool. ATPG(SAF, TDF)and MBISTverification usingunit delay and min/maxtiming cornersimulations. Workwith the Product/Testengineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting postsilicondebug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG,MBISTand bring-up on ATE. Developing,enhancingandmaintainingscripts as necessary Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Minimum of1-6yearsexperiencein ASIC/DFT- simulation andSilicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debugand yield enhancement In depthknowledge andhands-onexperience in ATPG-coverage analysis. In depth knowledge of Memory verification,repairand failure root-cause analysis. Experience withany of thesetoolsisrequired ATPG -TestKompress MBIST- MentorETVerify Simulation -VCS(preferred),modelsim. Expertisein scripting languages such asPerl, shell, etc is an addedadvantage Ability to work in an international team, dynamic environmentwithgood communicationskills Ability to learn and adapt to newtools,methodologies. Ability to do multi-tasking & work on several high priority designs in parallel