Memory Design Compiler

5 - 9 years

0 Lacs

Posted:1 week ago| Platform: Shine logo

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Work Mode

On-site

Job Type

Full Time

Job Description

You will be contributing/leading towards the design and development of Single/Multiport SRAM, Register file compilers in various technologies ranging from 28nm to 2FF. Your responsibilities will include: - Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder, and control logic. - Development of critical path and characterization flow for detailed margin and characterization simulations. - Statistical Analysis of Bit-Cell, Sense Amplifier, and Self Time Blocks for Compiler Target yield Sign-Off. - Design Tuning/optimizations to meet target PPA, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets. - Logic simulations and detailed timing analysis of key paths in high-speed memory design. - Good understanding and design experience of all the SRAM additional features and architecture options like low power features, redundancy features, and pipeline features. - Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design. Qualification Required: - Expertise in high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits. - Experience in Designing and Driving one or many Memory Compilers Specifications to final release. - Hands-on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis, and fixing. - Complete hands-on experience in using Cadence/Mentor schematic/layout editor tools. - Complete hands-on experience with Circuit simulation, MC analysis, and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, Nanotime, ESPCV, nWave, waveform viewer, etc. - Experience in Skill/Perl/Python Scripting is a strong plus. - Experience in Understanding the layout design issues in sub-nanometer regime is a Plus.,

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