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Memory Design Compiler UST

5.0 - 9.0 years

0 Lacs

karnataka

On-site

You will be contributing/leading towards the design and development of Single/Multiport SRAM, Register file compilers in various technologies ranging from 28nm to 2FF. Your responsibilities will include: - Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder, and control logic. - Development of critical path and characterization flow for detailed margin and characterization simulations. - Statistical Analysis of Bit-Cell, Sense Amplifier, and Self Time Blocks for Compiler Target yield Sign-Off. - Design Tuning/optimizations to meet target PPA, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets. - Logic simulations...

Posted 1 week ago

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