46 Hspice Jobs

Good understanding of signal integrity and power integrity principles Signal integrity extraction/3D models generation experience Cadence, HFSS and Siemens Advanced Solvers Expertise in circuit simulation with different tools such as Hspice, ADS, Cadence TopXp System level SI simulation using simulation tools Tools Used : Cadence PowerSI/ Agilent ADS/ Siemens Advanced Solver/Allegro SIP/Ansys SI wave, HFSS Expertise in circuit simulation with different tools such as Hspice and ADS. Experience Requirements 5-7 years of experience in SI/PI area Experience in board/package design SI/PI analysis Proven ability to use modern tools for S-parameter extraction of board/package Additional skills Programming language perl, tcl Ability to work in multi team environment

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Timing models for AMS macros in multiple formats as required. Review path, topology etc. reports Methodology and flow improvements using automation Characterization of Analog Mixed Signal macros Analog Digital interface timing model extraction Correlated timing model data to Hspice simulations for accuracy checks Follow QA checks for consistency and correctness. Skills Must have 3-4yrs hands-on exp in lib characterization for AMS macros. Must have experience with NanoTime Solid understanding of timing fundamentals. Experience in Hspice/Spectre simulators is desirable. Automation using shell/perl/tcl or python is a must. Nice to have Organized and methodical with effective communication skills.

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

We are looking for an IO Characterization Engineer with strong expertise in IO libraries and silicon validation. The candidate will work on advanced technology nodes, performing simulations, lab measurements, and delivering accurate characterization data for integration into sign-off tools. --- Responsibilities: Perform electrical characterization of IO circuits across process, voltage, and temperature (PVT) corners. Conduct silicon validation, ESD testing, signal integrity, and high-speed IO measurements. Develop automation scripts (Python/Perl/TCL) for data processing and analysis. Generate and validate timing, power, noise, and IBIS models for IO libraries. Debug and resolve silicon vs. simulation mismatches. Collaborate with design, CAD, and verification teams to improve IO quality and performance. --- Required Skills: 38 years of IO Characterization / IO Circuit Design experience. Proficiency in SPICE simulations and silicon measurement equipment (oscilloscopes, VNAs, BERT, etc.). Strong knowledge of CMOS IO design, ESD concepts, and signal/power integrity. Hands-on experience with IBIS, Liberty, HSPICE modeling flows. Expertise in Python, Perl, or TCL scripting for automation. --- Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical Engineering, or VLSI.

Join our ambitious team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our mission is to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You will have the opportunity to work on groundbreaking products and collaborate with talented hardware and software engineers to create disruptive infrastructure solutions that excite our customers. We are seeking talented engineers experienced in physically implementing large-scale networking and computing semiconductor products. You will be part of a dynamic startup environment and contribute to the full lifecycle of complex chip development, from CAD tool flow setup to physical verification and tapeout. This role is based in India, with options for hybrid/remote work. Candidates capable of in-office participation in Hyderabad or Bangalore are preferred. Responsibilities: - Develop and maintain the CAD tool flow for physical implementation in a cloud-first environment. - Collaborate with architects on chip-level floorplan and block partitioning, considering tradeoffs in functional partitioning and interface complexity. - Design major physical structures like clock architecture, power delivery network, and interconnect topologies. - Execute physical implementation at block, cluster, and top levels, including synthesis, floorplan, timing closure, and tapeout. - Liaise with foundry and library partners on 3rd party IP integration and process technology issues. Skills/Qualifications: - Proven track record in physical implementation of high-performance network switching/routing fabrics, NICs, CPUs, or GPUs in the latest silicon process nodes. - Proficiency in CAD tools like Cadence Genus, Synopsys ICC2, and analysis tools such as Redhawk. - Experience with scripting languages like Perl, Python, and SystemVerilog. - Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience with products shipped in high volume. Company Background: We are a well-funded startup based in Mountain View, CA, founded by industry veterans and backed by top-tier investors. Our diverse team excels in co-designing hardware/software solutions and has a proven track record in processing global data center traffic. Note: The above job description is based on the mentioned details in the provided job description.,

Qualcomm India Private Limited is at the forefront of technology innovation, breaking boundaries to enable next-generation experiences and driving digital transformation for a smarter, connected future. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is key to developing solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in a related field is also accepted. As an experienced STA/Timing Engineer with 3-10 years of hands-on experience, you will focus on timing sign-off and convergence for complex SOCs. Immediate involvement in timing analysis and sign-off with PD/Methodology teams across different sites and technology nodes is expected. Key responsibilities include: - STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. - Timing analysis, validation, and debug across multiple PVT conditions using tools like PT/Tempus. - Running Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. - Evaluating timing methodologies/tools on different designs and technology nodes. - Developing automation scripts within STA/PD tools for methodology enhancement. - Proficiency in TCL/Perl/Python for design automation and familiarity with digital flow design implementation. - Knowledge of process technology enablement, including circuit simulations and Monte Carlo. Preferred qualifications and skills include: - Expertise in STA timing analysis, AOCV/POCV concepts, CTS, and managing timing constraints. - Hands-on experience with STA tools like Prime-time and Tempus at Chip-level and Hard-Macro level. - Understanding of crosstalk noise, Signal Integrity, Layout Parasitic Extraction, and ASIC back-end design flows. - Proficiency in scripting languages such as TCL, Perl, and Python. - Basic knowledge of device physics. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. For more information or accommodation requests, please contact disability-accommodations@qualcomm.com. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes through Qualcomm's Careers Site. If you are ready to be part of a dynamic team pushing technological boundaries, apply now to join Qualcomm as a Hardware Engineer.,

As an EBU Application Engineer at Micron Technology, your main responsibility will be to develop and maintain technical product documentation. This includes creating design documentation, datasheets, product training materials, and migration guides. You will serve as the subject matter expert on product specifications, conduct design reviews, and collaborate with internal teams to assess the feasibility of new product features and their market relevance. Additionally, you will be the primary point of contact for questions regarding the specifications, operation, and utilization of Micron's DRAM devices. Your role will involve enabling Micron's DRAM technology in various market segments through product trainings, assisting with customer inquiries, reviewing designs, and addressing new system implementation issues. You will act as a bridge between customers and Micron's internal technical teams. Your tasks and responsibilities will include: - Creating and managing technical documentation - Developing internal design documentation for future products in collaboration with design engineering - Validating and documenting new product capabilities and customer-specific requirements - Creating and maintaining EBUs design addendum and product datasheets - Crafting technical notes to simplify complex DRAM topics for better understanding You will also be responsible for developing and delivering technical training materials, presenting at technical conferences, managing technical customer support, evaluating Micron's position for legal matters, monitoring qualifications, defining new products, and collaborating with internal teams and external customers to meet product requirements. The ideal candidate should possess the following skills: - Fluent in English - Strong communication skills, both written and verbal - Excellent presentation skills - Strong interpersonal skills - Self-directed and tenacious - Ability to understand and debug complex technical problems - 3 or more years of DRAM experience Additionally, favorable skills include a background in DRAM design, DRAM product engineering, or DRAM test engineering, knowledge of semiconductor testing philosophy and documentation, experience with Adobe FrameMaker, Verilog, HSPICE, thermal modeling, and PDN analysis. The educational requirement for this role is a BSEE/BSCE or equivalent degree. Micron Technology, Inc. is a leading provider of innovative memory and storage solutions, dedicated to transforming how information enriches people's lives. The company's commitment to customer focus, technology leadership, and operational excellence enables the delivery of high-performance DRAM, NAND, and NOR memory and storage products through the Micron and Crucial brands. Micron's innovations in the data economy drive advancements in artificial intelligence and 5G applications, shaping opportunities across various sectors. For more information, please visit micron.com/careers. If you require assistance with the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all relevant laws, regulations, and international labor standards.,

As an Analog Design Engineer at our company, you will utilize your 6+ years of experience to design and develop high-speed SerDes systems for CHIP to CHIP Communication interfaces. You will be responsible for creating and validating high-performance, low-power analog circuits, focusing on core analog building blocks such as RC circuits, Operational Amplifiers, Bandgap References, Comparators, and more. Your role will also involve architecting and implementing components like Phase-Locked Loops, Voltage/Current Controlled Oscillators, and Charge Pumps. Collaborating closely with layout, digital, and verification teams, you will design and simulate analog blocks in advanced CMOS nodes, ensuring attention to power, area, and performance. Additionally, you will participate in silicon bring-up, validation, and debug processes while documenting design specifications, simulation results, and test plans. To excel in this role, you should hold a Bachelors/Masters/PhD in Electrical Engineering or a related field, demonstrating a strong grasp of analog fundamentals and building blocks. Proficiency in analog simulation tools like Spectre, HSPICE, MATLAB, and Cadence Virtuoso is essential. Experience with mixed-signal verification, CMOS process, and high-speed SerDes systems (e.g., PCIe, USB, Ethernet) will be advantageous. Furthermore, any prior work on PAM4-based Tx/Rx designs, tapeout experience with high-speed analog/mixed-signal IP, or hands-on experience with lab testing and debug tools (e.g., oscilloscope, BERT, VNA) will be highly valued. Join our world-class engineering team to innovate in cutting-edge communication technologies, work on rewarding projects with industry impact, and enjoy competitive compensation, benefits, and career growth opportunities.,

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Timing models for AMS macros in multiple formats as required. Review path, topology etc. reports Methodology and flow improvements using automation Characterization of Analog Mixed Signal macros Analog Digital interface timing model extraction Correlated timing model data to Hspice simulations for accuracy checks Follow QA checks for consistency and correctness. Skills Must have 3-4yrs hands-on exp in lib characterization for AMS macros. Must have experience with NanoTime Solid understanding of timing fundamentals. Experience in Hspice/Spectre simulators is desirable. Automation using shell/perl/tcl or python is a must. Nice to have Organized and methodical with effective communication skills.

We are seeking a Mixed-Signal/Analog/IO Circuit Design Engineer who is enthusiastic about joining a rapidly expanding team of innovative circuit design engineers dedicated to advancing high-speed SerDes solutions. NVIDIA has continuously evolved over the past two decades, with groundbreaking inventions such as the GPU in 1999 that transformed PC gaming, modern computer graphics, and parallel computing. More recently, our GPU deep learning technology has sparked the era of modern AI, shaping the future of computing. At NVIDIA, we are committed to amplifying human creativity and intelligence, constantly adapting to new challenges and opportunities that have a meaningful impact on the world. Your responsibilities will include: - Designing Mixed-Signal/Analog circuits for High-Speed I/O Interfaces - Developing and implementing high-speed interfaces and analog circuits using cutting-edge CMOS FinFET processes - Defining circuit requirements and completing the design process from schematic creation to layout, verification, and characterization - Optimizing designs to meet system performance specifications We are looking for candidates with the following qualifications: - Experience in TX/RX related design or familiarity with high-speed SerDes/analog circuit design concepts - CMOS Analog/Mixed Signal Circuit Design Experience in deep sub-micron processes, particularly in FINFET - Proficiency in Cadence custom design tools, various circuit simulators like Hspice, XA, FineSim, Spectre - Ability to craft test bench environments for component and top-level circuit verification - Knowledge of Verilog, Verilog-A, Matlab, or similar tools for behavioral modeling of analog and digital circuits is a plus - Strong debugging and analytical skills - Excellent interpersonal skills, team player, and strong desire to collaborate effectively - Minimum bachelor's degree in Electrical Engineering or pursuing a Master's degree NVIDIA offers competitive salaries and a comprehensive benefits package, making us one of the most sought-after employers globally. Our company is home to some of the brightest and most talented individuals in the world. If you are a creative, independent thinker who thrives in a fast-paced environment, we encourage you to apply. --- As an SRE at NVIDIA, you will be responsible for: - Providing scalable and robust service-oriented infrastructure automation, monitoring, and analytics solutions for NVIDIA's on-prem and cloud-based GPU infrastructure - Managing the entire life cycle of new tools and services, from requirements gathering to design documentation, validation, and deployment - Offering customer support on a rotational basis We are looking for candidates with the following qualifications: - Minimum of 3 years of experience in automating and managing large-scale distributed system software deployments in on-prem/cloud environments - Proficiency in any programming language such as Go, Python, Perl, C++, Java, or C - Strong command of terraform, Kubernetes, and cloud infrastructure administration - Excellent debugging and troubleshooting skills - Strong interpersonal and written communication skills - Bachelor's degree in Computer Science or a related technical field involving coding (e.g., physics or mathematics) To excel in this role, you should: - Have the ability to break down complex requirements into manageable tasks and leverage existing solutions for implementation - Prioritize unit testing and benchmarking in your coding practices - Demonstrate the capability to select the most suitable algorithm to address scalability and availability challenges effectively NVIDIA is renowned as one of the most desirable employers in the technology industry, attracting forward-thinking and dedicated individuals. If you are a creative and independent thinker, we want to hear from you!,

Position: IO Design Engineer (SI510FT RM 3539) Job Description: Bachelors/Masters degree in Electronics & Communication/Electrical engineering Working experience (5 to 10 years) in IO Design Hands-on experience in TX and RX design architectures for high speed applications such as DDR4, full custom high speed design such as DDR PHY or SERDES along with timing budget analysis Experience in high-speed design techniques including SERDES , equalization etc. will be added advantage Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc. Should have good understanding of ESD phenomenon, familiarity in ESD circuits design and associated ESD guideline. Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies Experience in creating EDA model such as Verilog model, Liberty etc. will be of added advantage Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 5nm and the associated DSM issues Very analytical in nature and able to work in a multi-disciplinary environment Strong theoretical background with a pragmatic approach Good documentation and presentation skills High level of integrity and commitment to quality and timelines Job Category: Others Job Type: Full Time Job Location: Bangalore Experience: 5 - 10 years Notice period: 0-30 days

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Responsibilities include: In this position the individual will be responsible for designing, modifying and evaluating CMOS circuit structures for the most advanced high-performance low-power 3-dimensional NAND flash memory Verify designs in simulation and interact with layout, logic and other functional groups for implementation, full chip integration and silicon validation. Evaluation of these circuits will be done through FINESIM and VERILOG simulations. Collaborate with characterization engineers to fully characterize silicon, and partner with other designers to develop solutions for silicon issues Responsible for full chip silicon evaluation through probing. Interact with Memory Device team for transistor models, EDR/GDR requirements and tradeoffs. CMOS transistor level design, simulation, layout knowledge of common custom circuits like amplifiers, current mirrors, level shifters, switches, decoders. Knowledge of running and debugging Verilog simulations Good understanding of Solid-State device physics. Comfortable with IC tools such as Cadence analog design environment, HSPICE/FINESIM, VCS/EXCELIUM, UNIX. Ability to troubleshoot and analyze complex problems. Excellent communication skills to effectively collaborate with Off-site counterparts across global teams Qualifications B.E./B.Tech/M.E/M.S/M.Tech in electronics branches Aggregate of 75% & Above in all qualifying exams 4+ years of relevant Industry Experience Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools. With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges. You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions. Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff. As a team player, you communicate effectively, share knowledge openly, and support your peers in achieving shared goals. You value diversity, equity, and inclusion, and are eager to contribute to a culture that fosters creativity and personal growth. If you are ready to challenge yourself, make an impact, and be part of a world-class engineering team, Synopsys is the place for you. What Youll Be Doing: Developing and maintaining scripts and automation flows using TCL, Python, and Make to streamline EDA tool operations and design processes. Performing advanced timing, power, and noise analysis on CMOS circuits, leveraging your understanding of setup/hold constraints and leakage concepts. Contributing to the characterization of standard cell libraries, including NLDM/CCSN and LVF methodologies, and ensuring accurate modeling for signoff. Collaborating with design, verification, and methodology teams to optimize PPA (Power, Performance, Area) and address STA (Static Timing Analysis) challenges. Utilizing tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim to support verification, synthesis, and signoff activities. Participating in root cause analysis of timing and power issues, implementing innovative solutions, and documenting best practices for future projects. Staying abreast of the latest trends in AI/ML and exploring their application in EDA tool flows and design optimization. The Impact You Will Have: Accelerate the delivery and quality of Synopsys' IP and design solutions through automation and process innovation. Enhance product reliability by ensuring precise timing and power characterization, directly influencing customer satisfaction. Drive cross-functional collaboration, sharing insights and solutions that elevate team performance and project outcomes. Contribute to the adoption of cutting-edge AI/ML techniques, positioning Synopsys as a leader in intelligent EDA workflows. Reduce design cycle times and resource bottlenecks through effective scripting and workflow optimization. Mentor and support junior engineers, fostering a culture of knowledge sharing and continuous improvement. What Youll Need: 2-3 years of experience in VLSI design, EDA tool flows, or related semiconductor engineering roles. Proficiency in TCL, Python, and Make for scripting and automation. Strong understanding of CMOS circuit fundamentals, including timing (setup/hold), power (leakage/dynamic), and noise analysis. Experience with cell library characterization methodologies (NLDM/CCSN, LVF) and familiarity with library constructs and syntax. Working knowledge of STA analysis, PPA trends, and basic understanding of PNR (Place & Route). Hands-on experience with EDA tools: VCS, Design Compiler, Primetime, HSPICE/Primesim. Who You Are: Analytical thinker with strong problem-solving skills and a passion for innovation. Effective communicator, able to collaborate across disciplines and share complex ideas clearly. Self-motivated and adaptable, eager to learn new technologies and methods. Detail-oriented with a commitment to delivering high-quality results under tight deadlines. Team player who values diversity, equity, and inclusion in the workplace. The Team Youll Be A Part Of: You will join a vibrant team of R&D engineers focused on advancing the state of the art in chip characterization, timing, and power analysis. Our team collaborates closely with cross-functional partners in design, verification, and methodology to deliver next-generation semiconductor solutions. We foster a culture of innovation, mentorship, and continuous improvement, ensuring every member has an opportunity to grow and make a meaningful impact. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Are you ready for a career that presents challenges while also instilling a sense of pride in your work At Ambit, we provide an ideal platform for individuals to work and advance in the field of semiconductor design. Our employees enjoy the freedom to work in their own adaptable ways, with the necessary support to continue learning and improving their skills. We firmly believe that in order for a company to achieve significant growth through innovation, its employees must be empowered to experiment and innovate freely. The positive and vibrant work environment at Ambit reflects our management's dedication to our employees and their values. Join us today for a promising future in semiconductor design services. Qualification: - B.Tech / M.Tech or equivalent from a reputable University Experience: - 7 - 10 years of relevant experience Responsibilities: - Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs. - Conduct timing analysis, validation, and debugging across various Process-Voltage-Temperature (PVT) conditions using tools like Primetime and Tempus. - Utilize Primetime and/or Tempus for STA flow optimization and establish Spice to STA correlation. - Assess different timing methodologies and tools across various designs and technology nodes. - Develop automation scripts within STA and Physical Design (PD) tools to enhance methodologies. - Demonstrate proficiency in technical writing and communication skills while being open to working in a collaborative environment. - Experience in design automation using TCL/Perl/Python. - Knowledgeable in digital flow design implementation from Register Transfer Level (RTL) to Graphic Data System (GDS) using tools like ICC, Innovous, PT/Tempus. - Familiarity with process technology enablement including circuit simulations with tools such as Hspice/FineSim and Monte Carlo simulations. Join Ambit today and be part of an innovative team dedicated to semiconductor design excellence.,

As a Senior R&D Engineer at Synopsys, you will play a crucial role in characterizing and modeling standard cells for various technologies and foundries. Your deep knowledge of MOSFET and FINFET technologies will be instrumental in conducting quality analysis of characterized liberty and Verilog models, ensuring accuracy in terms of timing, power, and functionality. By validating characterization and simulation tool versions, you will contribute to the enhancement of our standard cell models and tools" reliability. Your commitment to providing daily status updates and ensuring on-time, high-quality releases will be essential in driving innovation and continuous improvement within our engineering processes. Your collaborative nature and excellent communication skills will enable you to work effectively within and outside your team, making significant contributions to our projects. Your responsibilities will include applying your expertise in MOSFET and FINFET technologies, characterizing standard cells, conducting quality analysis of liberty and Verilog models, validating characterization and simulation tools, and providing daily status updates for project transparency. Your proactive approach, attention to detail, and commitment to meeting deadlines will be key in delivering high-quality results. You will be part of a highly skilled and motivated engineering team dedicated to ensuring the accuracy, reliability, and quality of our standard cell models and tools. Together, we will drive innovation and continuous improvement in our processes, making significant contributions to the advancement of technology applications. Join us at Synopsys to transform the future through continuous technological innovation. Explore the comprehensive range of health, wellness, and financial benefits we offer, tailored to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.,

You will be responsible for DDR and LPDDR design and analysis, as well as high-speed serial IO design and analysis for interfaces such as PCIE, USB, UFS, CSI/DSI/MIPI. Power Integrity analysis will also be a significant part of your role, utilizing SI/PI tools including Ansys HFSS/SIwave, Cadence/Sigrity, Keysight ADS, HSPICE, as well as spreadsheets and similar productivity tools. You will also work with Mentor or Cadence board design tools. Your primary focus will be on performing SI/PI analyses to address signal and power integrity challenges. Collaboration across organizational boundaries will be crucial, along with effectively documenting and presenting results. You will work closely with an experienced SI engineer, applying established PSIG methodologies and contributing to the evolution of analysis methodologies. Key responsibilities include conducting various IO analyses using established methodologies, covering DDR memory interfaces and a range of serial interfaces. You will analyze and provide design guidance for DIE floor plans, IC packages, and PCB power distribution networks. Furthermore, you will be responsible for documenting, distributing, and presenting results at relevant meetings. To be successful in this role, you should have at least 4 years of work experience in areas such as electromagnetic theory and transmission lines, basic signal and power integrity concepts, commercial 3D electromagnetic field solver, commercial SI or RF simulation and analysis tools, and SPICE transient simulation including the use of IBIS models. At GlobalLogic, we prioritize a culture of caring where people come first. You will experience an inclusive environment focused on acceptance and belonging, fostering connections with collaborative teammates, supportive managers, and compassionate leaders. We are dedicated to your continuous learning and development, offering various opportunities to enhance your skills and advance your career. You will engage in interesting and meaningful work, collaborating on impactful projects that challenge your problem-solving skills. We believe in balance and flexibility, providing different career areas, roles, and work arrangements to help you achieve a harmonious work-life balance. As a high-trust organization, we value integrity and trust, ensuring a safe, reliable, and ethical environment for our employees and clients. GlobalLogic, a Hitachi Group Company, is a leading digital engineering partner to top global companies. Since 2000, we have been driving the digital revolution by creating innovative digital products and experiences. Collaborating with clients worldwide, we focus on transforming businesses and industries through intelligent products, platforms, and services.,

We are looking for a highly skilled and experienced Lead Engineer to join our team and contribute to the verification of mixes Signal. The ideal candidate should have a deep understanding of the Cadence, AMS along with expertise in system-level development and debugging What You Will Do Proficient in Verilog-AMS, System Verilog, and UVM methodologies Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What You Need to Be Successful Proficient in Verilog-AMS, System Verilog, and UVM methodologies Bonus Points if You Have Experience with Cadence Spectre or similar AMS simulation tools Strong understanding of analog circuit design principles (op-amps, transistors, etc.) What Makes You Eligible An accomplished leader with a minimum of 8+ years of experience in software design & development and a Bachelor's Masters degree Excellent communication skills (written/verbal) & Team spirit Risk taker with passion for innovation Autonomous working to explore new technologies *Mandatory Key Skills analog circuit design,software design,software development,Cadence Spectre,mixed signal verification*,Cadence*,AMS*,Verilog*,System Verilog*

As a Senior Base STD Characterization Engineer, you will work in a highly innovative, motivated, young, and dynamic design team capable of verifying complete products using state of the art STD Cells , Custom Cells on latest CMOS process technology Job Description Responsibilities Silicon smart based STD cell characterization experience. Writing vector/ARC for STD Cells Responsibilities for hspce (hspice/spectre) based characterization. Circuit understanding Basic building blocks - AND , NAND , NOR , latches , flops design understanding Block level circuit simulation , Analysis capability STD cell timing checks - linearity , monotonicity , QA experience Analysis of Circuits , Timing concepts schematic analysis Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Opportunities to work closely with cross functional groups such as Product Engineering and Design Architecture. May also review vendor capability to support product development. 3-5 years of experience

Description: DDR and LPDDR design and analysis High speed serial IO design and analysis, PCIE, USB, UFS, CSI/DSI/MIPI Power Integrity analysis SI/PI tools :Ansys HFSS/SIwave, Cadence/Sigrity, Keysight ADS, HSPICE Spreadsheets and similar productivity tools Mentor or Cadence board design tools Requirements: The candidate is expected to perform SI / PI analyses and provide guidance on signal and power integrity challenges. Working effectively across organizational boundaries is essential as is the effective documentation and presentation of results. The candidate is expected to work closely with an experienced SI engineer while applying established PSIG methodologies. The engineer will have the opportunity to influence the evolution of analysis methodologies. Job Responsibilities: Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include DDR memory interfaces and variety of serial interfaces. Analyze and provide design guidance for DIE floor plans, IC packages, PCB power distribution networks using established methodologies. Document, distribute, and present results at appropriate meetings. 4+ years of work experience in the following areas: Electromagnetic theory and transmission lines Basic signal and power integrity concepts Commercial 3D electromagnetic field solver Commercial SI or RF simulation and analysis tools SPICE transient simulation including use of IBIS models What We Offer: Exciting Projects: We focus on industries like High-Tech, communication, media, healthcare, retail and telecom. Our customer list is full of fantastic global brands and leaders who love what we build for them. Collaborative Environment: You Can expand your skills by collaborating with a diverse team of highly talented people in an open, laidback environment — or even abroad in one of our global centers or client facilities! Work-Life Balance: GlobalLogic prioritizes work-life balance, which is why we offer flexible work schedules, opportunities to work from home, and paid time off and holidays. Professional Development: Our dedicated Learning & Development team regularly organizes Communication skills training(GL Vantage, Toast Master),Stress Management program, professional certifications, and technical and soft skill trainings. Excellent Benefits: We provide our employees with competitive salaries, family medical insurance, Group Term Life Insurance, Group Personal Accident Insurance , NPS(National Pension Scheme ), Periodic health awareness program, extended maternity leave, annual performance bonuses, and referral bonuses. Fun Perks: We want you to love where you work, which is why we host sports events, cultural activities, offer food on subsidies rates, Corporate parties. Our vibrant offices also include dedicated GL Zones, rooftop decks and GL Club where you can drink coffee or tea with your colleagues over a game of table and offer discounts for popular stores and restaurants!

GlobalFoundries is currently seeking a highly motivated Memory Design Engineer to join the Memory IP group in the Global Organization, located in Bangalore. In this role, you will be responsible for developing CMOS memories such as SP SRAM, DP SRAM, Register File, and ROM. Your tasks will include circuit design, simulation, margining, and characterization of full custom circuits, as well as functional simulations and statistical analysis. You will also be involved in verifying bit cells, physical layout design and verification, and signing off and releasing the memory IPs on dedicated IP validation test chips. Additionally, you will support silicon bring-up and characterization, participate in implementation & design/layout reviews, and contribute innovative ideas for addressing design problems. Collaboration with IP design and layout teams will be a key aspect of this role. The ideal candidate should hold a Bachelors/Master's degree in Electrical (VLSI, Microelectronics, or related fields) from a reputable university with a minimum of 4-12 years of work/industry experience. Proficient knowledge and experience with EDA tools such as Cadence, Mentor Graphics, and Synopsys for schematic design & simulations are required. Experience in SRAM Memory designs, timing characterization, and Verilog is desirable. General analog mixed-signal design concepts knowledge is also preferred. Strong technical verbal and written communication skills are essential, along with the ability to work effectively with cross-functional teams. Preferred qualifications include knowledge in various technologies (Bulk, CMOS & SOI) process, hands-on experience with state-of-the-art memory or analog design flows, and programming skills applicable to design flow automation tasks. The ability to work within a dynamic interdisciplinary environment, knowledge of different technology nodes, and proficiency in communicating and working efficiently in an international multi-disciplinary setting are advantageous. Strong analytical and problem-solving skills are a must. GlobalFoundries is an equal opportunity employer that values diversity and inclusion in the workplace. We believe that a multicultural environment enhances productivity, efficiency, and innovation, while ensuring that all employees feel respected, valued, and heard. For more information about our benefits, please visit: https://gf.com/about-us/careers/opportunities-asia,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished analog design engineer with a passion for advancing technology and enabling world-class silicon solutions. With over5 years of hands-on experience in custom analog design, you have mastered the nuances of analog circuit building blocks, including amplifiers, reference circuits, and clock generators. You thrive in collaborative environments, working seamlessly with design and CAD teams to refine simulation methodologies that elevate design verification efficiency. Your technical toolkit is robust, featuring expertise in industry-standard verification and simulation tools such as HSPICE, Primesim, and VCS, as well as proficiency in scripting and automation using Perl, Python, and TCL. Your approach is both analytical and creativeyou relish the challenge of optimizing analog circuits for performance, reliability, and scalability. You are also an effective communicator, eager to share your knowledge through peer support and training, thereby fostering a culture of innovation and continuous learning. Your adaptability ensures you stay at the forefront of evolving industry trends and methodologies, and your proactive mindset drives you to seek out opportunities for process improvement. Above all, you believe in the power of teamwork and mentorship, empowering those around you to achieve collective success. What Youll Be Doing: Designing, developing, modifying, and evaluating physical IP such as SERDES, DDR, and Memory. Collaborating with design and CAD teams to develop and deploy advanced simulation methodologies. Automating design and simulation flows/tasks using scripting languages and existing tools. Providing technical support and training to team members to enhance overall capabilities. Analyzing and optimizing analog circuit building blocks, including amplifiers, reference circuits, and clock generators, for performance and efficiency. Ensuring efficient use of verification tools to accelerate and improve the accuracy of design verification processes. The Impact You Will Have: Enhancing the efficiency and accuracy of analog design verification, leading to faster, more reliable silicon development. Contributing to the creation of cutting-edge high-performance silicon chips and software content that power next-generation technologies. Driving innovation in analog circuit design and simulation methodologies, setting industry benchmarks. Streamlining the design and development cycle, reducing time-to-market for critical IP blocks. Building team expertise through training and support, fostering a collaborative and high-performing culture. Playing a pivotal role in the continued success and technological leadership of Synopsys. What Youll Need: BE/MTech in Electronics or a related field. 5+ years of proven experience in Custom Analog Design. Proficiency with industry-standard design verification and simulation tools (HSPICE, Primesim, VCS). Strong scripting and automation skills using Perl, Python, and TCL. In-depth knowledge of analog circuit building blocks, including amplifiers, reference circuits, and clock generators. Who You Are: A collaborative team player who excels in cross-functional environments. An effective communicator with the ability to share complex technical concepts clearly. A problem-solver with keen attention to detail and a drive for innovation. A proactive learner who actively seeks out new technologies and methodologies. A mentor and coach who supports the growth and development of colleagues. An analytical thinker skilled at evaluating and addressing complex engineering challenges. The Team Youll Be A Part Of: You will join a dynamic and innovative team dedicated to analog design and verification. Our culture thrives on collaboration, creativity, and continuous improvement. We work closely with multiple departments to ensure seamless integration and optimal performance of our products, playing a significant role in Synopsys broader technology strategy and success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including LDO, PLL, DLL, Rx, Tx and clocking circuits Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: spectre, finesim, hspice & other flows Good automation & scripting knowledge is plus. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including LDO, PLL, DLL, Rx, Tx and clocking circuits Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: spectre, finesim, hspice & other flows Good automation & scripting knowledge is plus. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. NAND Flash Design knowledge is plus Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including DLL, Rx, Tx and clocking circuits Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: finesim, hspice & other flows Good automation & scripting knowledge is plus. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Meeting the unique challenges posed by various target applications, SLM enables differentiated products to market quickly with reduced risk We are seeking an experienced, initiative-taking, and high-calibre individual to join our SLM Monitors group as a Monitor IP Design, Architect Someone who thrives in a collaborative environment and has a passion for creating innovative technology Have a strong technical background in Custom Circuit design, System Design, methodologies and tools and is adept at working with advanced finfet / GAA process challenges Proactive analytical person with a keen eye for detail and a dedication to delivering high-quality results Excellent communication and people skills and can collaborate effectively with internal teams and external customers Driven by a desire to innovate and contribute to the success of our innovative technology products Job Descriptions Looking forward to work on conceptualizing, designing and productizing state of the art Monitor IP to be used in SLM monitors realized though ASIC design flow Work on Architecting sensing elements for on-chip Process, Voltage, Temperature, glitch and Droop monitors for monitoring silicon biometrics You will be the part of SLM team Individual should have strong technical experience in full custom mixed-signal circuit design, circuit simulations, working knowledge of custom layout, and pre-post-silicon characterization Additional responsibilities include: Development of statistical simulation methodologies Liaising with layout team to achieve best possible design solution End to end ownership of the designed custom cells Deployment of new circuits into test chips and post-silicon characterization Architecting new sensors and enhancing existing ones through collaboration with other architects and stakeholders Building and refining design flows to enhance efficiency and effectiveness Conducting pre and post-layout simulations and characterization across various design corners Ensuring designs meet advanced finfet / GAA reliability and aging, reliability and Automotive grade requirements Working closely with the RTL, Verification and Physical Design teams for ensuing integration and Quality Owning the product from Spec to Silicon report Preferred skills: Strong custom design experience specification, circuit design description and schematics Strong understanding of device Physics and Can work independently and debug and provide circuit solutions Hands on experience with circuit design & simulation tools, IC design CAD packages from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies Job Requirements BS or MS degree in Electrical Engineering with 15+ years of relevant industry experience Sound knowledge of custom / Standard cell design methodologies, layout tools, and physical verification Familiarity with advanced finfet / GAA process challenges, simulation techniques and modeling