About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Liquid Security Team part of Marvell MBE team (Multi Market Business group) primarily focuses on developing high quality software for HSM adapters deployed in leading Hyperscalers like Microsoft, AWS and many other customers. We are an ambitious team within a multi-site, multi-cultural company. Marvell develops challenging products and a unique high tech environment that encourages continued learning and growth. We are looking for technology passionate engineers with focus on execution and quality to help innovate and develop highly scalable software What You Can Expect Definition and implementation of product improvements, analyzing and troubleshooting deployment, configuration and product issues, proposing short term workarounds and implementing product fixes. Functional and technical design of the software, developing and validating entire functional components and modules, collaboration with the team on integrating the product and its infrastructure, code reviews and improvement of the software development processes. Collaborate with Support, R&D and Technical marketing Engineers to diagnose and troubleshoot escalated customer issues and orchestrate development and testing of patches/hot-fixes. What We're Looking For A bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field, with 5 to 10 years of relevant industry experience. Solid grounding in cybersecurity and data protection, including symmetric/asymmetric cryptography, key management, and secure communication protocols. Strong grasp of data structures, algorithms, and software design principles. Expert-level programming skills in C/C++, with extensive experience in development and debugging of low-level software. Good understanding on Linux kernel internals, device drivers, and socket programming Proven experience in embedded systems design and development, ideally in a security-focused context. Demonstrated curiosity and passion for learning new technologies and solving complex technical challenges. Proficient in using AI-powered development tools (e.g., GitHub Copilot, Microsoft Co-Pilot) to enhance productivity, improve code quality, and support AI-assisted testing and automated code generation. Preferred Skills Experience with cryptographic system design, including PKI, certificate management, attestation, and hardware-backed security using TPM or HSM. Working experience with Rust programming in production-level environments. Working experience integrating or developing for HSM adapters is a notable benefit Experience working with Secure Boot and OP-TEE for secure firmware and application execution Strong problem-solving and analytical skills. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Goal Of Section Convey impact of the business group they will be joining on Marvell and the world. Questions To Answer In This Section What can’t Marvell do if they do not have this team to execute? What projects is this team responsible for delivering? What do they work on every day? Why should you work on this team vs another team doing the same project at another company? How is this technology used in the world that most people would recognize? What You Can Expect The new hire will start with documenting software drivers, that are published in HTML. We are tracking software updates in JIRA. An engineer, usually an application engineer, will document the change and the technical writer needs to be able to track the documentation progress and then format it into the correct location in the user guide. Today we use FrameMaker as the main authoring tool, so the technical writer takes the engineering update, and places it in the correct location in the user guide, taking care of the formatting aspects. The new hire needs to understand if the content “makes sense," so the outcome is understood by the customer. Every update to the documentation goes through a review by a few engineers. What We're Looking For BTech/MTech with 8 to 12 years of relevant experience. The ideal candidate will have experience working in engineering environments and be proficient in various documentation tools. Skilled technical writer with a background in creating engineering documents for both hardware and software. The candidate must know and work with Adobe FrameMaker, Microsoft Word, Power Point, Excel and Visio. A candidate must be familiar with structured technical writing methodology (DITA) Nice to have requirement is HTML publishing, Doxygen, knowledge of CSS The technical writers in our group must be able to manage their time and handle more than one task at a time. Interact directly with engineers, sit with them, understand and document their explanation. Should also be able to get engineering design documents and create customer-facing documents out of them. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Custom Compute and Storage (CCS) team develops silicon and software for some of the largest companies in the world in the growing datacenter, AI, enterprise and carrier markets. The Firmware team in the CCS BU focuses on developing and integrating key software components that enables use of silicon. These components form a critical subset of the complete software stack, ensuring the silicon's capabilities are effectively utilized. The team's work plays a key role in supporting the broader software ecosystem. What You Can Expect Primary responsibility is to design and develop software for Marvel's ARM64 based SoCs. Interact with customers to understand their requirements and add new features in firmware. Work closely with cross-functional teams (hardware, QA, marketing) across multiple locations. What We're Looking For Bachelor’s degree in computer science, Electrical Engineering or related fields and 6-12 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 4-10 years of experience. Sound knowledge on ARM64 architecture. Sound knowledge on ARM boot sequence, secure/non-secure software components and the exception levels they run at. Hands-on experience working on ARM trusted firmware (ATF), U-boot and Linux low speed peripheral drivers like SPI, I2C, MMC. Knowledge on ARM64 debug and error handling technologies like RAS, synchronous/asynchronous errors, watchdog etc. will be a big plus. PCIe protocol knowledge is a plus. Excellent C programming skills. Excellent software design, problem-solving, debugging and documentation skills. Prior hands-on experience on using GDB, logic analyzer, Lauterbach is a plus. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is a leading provider of innovative technologies, including high end Packet Processors running SONiC for Data Centers SONiC is an open source network operating system based on Linux that runs on switches from multiple vendors and ASICs. SONiC offers a full-suite of network functionality, like BGP and RDMA, that has been production-hardened in the data centers of some of the largest cloud-service providers. It offers teams the flexibility to create the network solutions they need while leveraging the collective strength of a large ecosystem and community. This Group is responsible for developing and qualifying SONiC based Platform for Marvell Packet Processors targeted for Data Center. What You Can Expect Hands-on experience in routing/switching abstraction interfaces like FPA, SAI or any OCP Hands-on experience with Network Operating system , SONiC or similar. Experience in handling Tier-1 customer requirements Datacenter or similar. Experience scripting languages such as Unix shell, Python, Perl or similar. Experience in management of high complex switching/routing lab infrastructure for Development activities. Experience in handling fault tolerant switch management areas such as High availability, DB persistency, Hitless software upgrade, In-Service software upgrade, etc Hands-on experience in L4 protocols such as TCP, UDP, etc Hands-on experience working with open source software Knowledge in Data center switches/network management areas – CLI, SNMP, Yang Models etc What We're Looking For Bachelors/Masters in CS/ECE/EE with 6 to 15 years of relevant work experience as Individual contributor (Technical leader/Architect) Extensive experience in handling complex data structures and algorithms in routing/switching software. Extensive technical depth in L2 and L3 Ethernet switching and routing protocols. Extensive experience in OS development experience in Switching/Routing ASIC Hands on experience on switch/router embedded system software development Experience architecting innovative, scalable Linux based Embedded products. Extensive experience in network programming languages such as C or equivalent. Extensive experience in Linux/Unix/FreeBSD/ network programming skills such as TCP/IP, socket programming Extensive experience in understanding requirements/architect/design of networking communications standard bodies like IEEE, IETF etc. Ability to deliver high quality features with extensive automation coverage, including experience applying test driven development methodology Demonstrated experience in developing multiple products from conception to shipping in Switching/Routing. Ability to communicate technical concepts to a wide range of audiences spanning executives to junior engineers Proven knowledge in SDLC of high complex and large software development – Waterfall, Agile, Extreme programming, or similar. Proven knowledge in Source version control of R&D internal and customer releases along with Continuous Integration methodologies. Working experience in L2 switching/forwarding areas such as LAG, VLAN, xSTP, LLDP, Link OAM, ARP, VxLAN, DC fabric switching, etc. Working experience in L3 unicast/multicast routing protocols such as RIP, OSPF, IGMP, BGP, ISIS, etc. Working experience in areas like ACL, QoS, Policers, TCAM, etc. Experience in chassis or pizza box-based switching/routing products. Working experience in UT framework such as google test or similar. Good experience in software repository tools GIT, SVN and Perforce Good experience in traffic testing tools IXIA, Wireshark, Scapy, Tcpdump or similar Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell switching solutions in NSX team have been driving a change in networks from the traditional methods of simply moving bits to delivering exciting services and applications. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell technology is powering the next‐generation network. What You Can Expect As a Design Verification Director, you’ll be responsible for - Lead a team of IP/SOC verification engineers, fostering a collaborative, innovative, and performance-oriented environment. Mentor staff members to nurture skills development and professional growth. Demonstrate excellent project management skills, capable of leading multiple projects simultaneously under tight deadlines. Proficient in collaborating with cross-functional teams and stakeholders across various sites. Demonstrate leadership and execute projects across a highly distributed engineering team. Responsible to mentor and train the team Manage the engineering resource allocation. Recruit, retain, and develop top engineering talent. Foster an inclusive, collaborative, and high-performance work environment. Manage all phases of verification stages, ensure project timelines are met or exceeded with quality standards. Responsible for the planning, execution, quality reviews and deliverables for Marvell switching products Oversee the validation of high-performance ASICs, IPs, and subsystems tailored for data center, wireless, and automotive applications. Collaborate with senior management to set engineering goals, align projects with business objectives, and advance the company’s market position. Technology Innovation. Stay abreast of industry trends and technological advancements to keep the company at the forefront of ASIC development. What We're Looking For Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. 20+ years of experience in ASIC verification, with at least 5 years in a leadership role managing verification teams. Strong knowledge of UVM/OVM/VMM, SVA and Formal verification Strong understanding of verification of tools and methodologies involved. Proven expertise in verification of ASICs for data centers, wireless communications, and/or automotive systems. Proficient in collaborating with cross-functional teams and stakeholders. Excellent communication and interpersonal skills. Strong knowledge of UVM/OVM/VMM, SVA and Formal verification Strong ability in scripting languages such as Perl, Python, Makefile, C Shell. Knowledge of power management and power simulation using UPF Responsible for the planning, execution, quality reviews and deliverables for Marvell switching products Demonstrate leadership and execute projects across a highly distributed engineering team. At least 5 years’ experience in direct management of very senior verification engineers. Preferred/Plus:Networking knowledge Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Staff Signal Integrity Engineer with Marvell, you’ll be a member of the Custom Compute & Storage - CCS BU. You’ll be part of the Signal integrity Team designing high performance hardware for the industry leading CCS-BU SoC products targeted for Datacenter, Storage and AI applications. Marvell Custom Compute & Storage - CCS BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast‐growing product lines, Marvell technology is powering the next‐generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Engage with Hardware Engineering, Package Design and SoC Design Teams to define the SI/PI requirements and dependencies with support. Perform pre-layout simulations and generate layout guidelines and checklists. Review schematics for the hardware and analyse the feasibility of hardware. Review design and guide PCB layout team for placement and layout for first-time-right design. Perform SI/PI simulation for the hardware and deliver error free reports. Measure fabricated PCBs and perform correlation between simulation and measured results. What We're Looking For Bachelor’s degree in Electrical Engineering and 4 - 8 years of related professional experience or Master’s/PhD in Electrical Engineering with 1-3 years of experience. Strong fundamentals in EM, transmission lines and microwave theory Experience in using 2-D and 3-D EM simulation tools such as Ansys HFSS, SI-Wave, Cadence Clarity, PowerSI. Experience on any of the schematic and layout tools - Cadence Allegro, Mentor Expedition, Orcad Ability to manage hardware development involving various cross functional teams like HW Design, PCB layout, Hardware assembly, IC packaging teams, Analog and Digital designers, marketing and PCB Fab vendors. Ability to automate the SI, PI and Packaging activities using scripting tools like Python, TCL. Power plane design, modeling and analysis using tools like PowerSI, Power DC, SIwave Working knowledge of circuit analysis tools: ADS, HSpice Frequency domain and time domain knowledge of high speed signaling Familiarity with PCB technologies, DFM, DFA, materials, stackup design rules and assembly rules Prior hands-on experience of reviewing Hardware Schematics and PCB layout on industry standard tools. Understanding, debugging and simulations of hardware design Experience with VNA and TDR measurements for PCB characterization would be a plus. Track record of new product introduction from concept, through development and production is a plus. Knowledge of the thermal analysis of the PCB hardware is a plus. Experience with channel simulations using MATLAB or ADS or other tools is a plus. Strong communication, presentation, and documentation skills Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is rapidly growing its compute business with innovative new controllers, adapters, accelerators, software development kits and full turnkey firmware offerings. We are an ambitious team within a multi-site, multi-cultural company. Marvell develops challenging products and a unique high tech environment that encourages continued learning and growth. As part of this growth, we are expanding our FW development teams in Pune. What You Can Expect As a senior member of the development team, you will collaborate with various teams, including SoC Design, SoC Validation, SQA, Field Application Engineers, and customers. Your responsibilities will encompass firmware design, implementation, qualification, and customer support, contributing as part of a global firmware team. Based in Pune, you will work closely with teams across different locations worldwide. What We're Looking For Education: BTech/MTech in Engineering with 8 to 16 years of relevant experience Technical Expertise Strong background in software/firmware engineering. Experience in developing storage products. Hands-on experience with firmware development in an SoC environment. Proficiency in C programming and embedded firmware tools/techniques. Familiarity with C++ and Python is a plus. Key Skills & Competencies Ability to work in a dynamic, fast-paced environment. Capability to technically lead the development of independent modules in a large firmware stack. Strong communication skills in English. Preferred Experience Secure boot and related security firmware protocols. Firmware development for PCIe HBA products. Working with NVMe, PCIe, Security, and TCG/Opal. Agile development methodologies. Knowledge of processor architectures, such as ARM. Designing and supporting firmware for mass production. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell's Custom compute silicon engineering group is a leading provider of innovative storage technologies, including ultra‐fast read channels, high‐performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD), solid‐state drive (SSD) and accelerators electronics markets. Many of the same technologies have been utilized in Marvell storage system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect Design and execute post silicon validation tests for SSD Chipsets, during R&D processes. Develop, port and execute bare metal SW to validate Storage SoC's. Job will involve Pre and Post Si testing of the bare metal functionality of the Storage SoC, including performance, and power The candidate will also review and prepare test plans and test results documentation. Develop testing and benchmarking applications. Analyze the test results and generate professional validation reports. Provide technical support to Field Application Engineers who support customers. Provide technical support to Test Engineers who design tests for mass production. What We're Looking For Bachelor’s degree in Electrical , Electronics or Computer Engineering, or a related field with 12+ years of experience. Master’s degree in Electrical , Electronics or Computer Engineering, or a related field with 10+ years of experience. We are looking for hardware validation/applications engineer with experience in Solid States Drive. The candidate should have prior experience interacting with customers. Proficient in C/C++ , Arm Assembly , 64 bit Arm CPU architecture. Experience in Firmware Development under Bare Metal/Linux Environment and Debugging on SoCs for embedded Applications Understanding of SSD controller is preferred Experience in interfaces like NAND/PCIe/NVMe/DDR is a plus Expertise with typical lab tools: Emulators, Oscilloscopes, Logic Analyzers Experience in analog characterization for power and high speed characterization is an added advantage. Good communication skills in English, written and spoken. Candidate should be flexible, proactive and have the ability to work across disciplines and manage time across several demands Should be able to work on a given task independently. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Custom and Compute Solutions Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. What You Can Expect Define the sub system architecture, micro-architecture and register specification for highly complex SoCs. Drive and participate in specification writeup Conduct detailed performance, architectural and design requirement reviews with cross-functional teams, IP Vendors and customers Implement a specification using RTL coding techniques and best practices Work with third party vendors to define customization requirements of third party IPs (controller, PHY, etc.) Work with the physical design teams, reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff. Work with the verification team on pre-silicon verification tasks such as reviewing the verification test plans, coverage analysis, full-chip simulation and emulation, performance and power analysis and debug Help develop and/or evaluate design and verification methodologies and participate in improving existing ones Collaborate with and provide guidance to the post silicon and software teams for prototype bring up and performance tuning Provide mentorship to the more junior team member What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 12 -20 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10-18 years of experience. Experience in creating architectural, micro-architectural, and register specifications. Verilog/System Verilog RTL coding with System Verilog assertions Well-versed in all stages of the ASIC design flow (including specification, architecture and design implementation, prototype bring-up) Expertise in high speed protocols (Ethernet). Should have worked on Full Chip Integration of Complex SoC design. Has worked on complex chips such as network processors, CPUs ,GPUs ,NOCs ,Switches , Machine Learning SoCs etc. owning full chip, subsystem and block level architecture and design Expertise in any of the following domains would be a big plus: networking, embedded systems architecture, computer architecture, machine learning accelerators Experience with scripting in Perl/Python/Shell Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN-Insertion/MBIST/ATPG/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs. Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products. As part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out What You Can Expect Build and Lead a strong technical team of emulation experts to define emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium. Work with various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc. Work closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team. Define and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation Interface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience. Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification. Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Siemens including extensive experience in building complex SOC emulation models Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM) Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms. Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products. As part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out What You Can Expect Build and Lead a strong technical team of emulation experts to define emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium. Work with various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc. Work closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team. Define and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation Interface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience. Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification. Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Siemens including extensive experience in building complex SOC emulation models Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM) Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms. Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, data center, and networking applications. What You Can Expect As a Senior Staff Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 9+ years of experience running an industry standard EDA tool for PnR signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation . Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

About Marvell . Your Team, Your Impact As member of the physical design team at Marvell you will have the opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design Signoff. Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff. Opportunity to work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more. What You Can Expect As a Principal Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 12+ years of experience running industry standard EDA tools for PnR signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position is for a Techno-Managerial role who will be responsible for Managing a team of skilled DFT-engineers who work on implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs. The management responsibilities include but not limited to handling career-development, mentoring and monitoring project execution. As a senior technical leader, the role also involves driving end to end DFT-execution on SoCs and Subsystems, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Management experience - Must have directly managed small sized teams , members HandsOn Working experience in various stages of DFT-Execution SCAN-Insertion / MBIST / ATPG / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus, Modus, NCSim / DC, Tessent, Spyglass/Tmax) Prior experience in Custom-ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelors degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN-Insertion / MBIST / ATPG / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs. Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus, Modus, NCSim / DC, Tessent, Spyglass/Tmax) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus

This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Work with a global team on the physical design of complex chips at Block/Partition/Full-Chip level. You will also play a critical role in refining the methodology to enable an efficient and robust design process working closely with the methodology team. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on a given hierarchical design at block/partition/full-chip level. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend team will be crucial to ensure successful tapeouts. Additionally, your involvement with the global timing team will include debugging and resolving any block/partition level timing issues encountered at the Chip level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 15+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs. In your coursework, you must have completed a course in digital electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e. g. , 7nm, 5nm, or below) is highly desirable. Working knowledge on any of the scripting in languages such as Perl, tcl, AWK and Python. Knowledge of Verilog/VHDL basics is an added advantage. Good communication skills and self-discipline contributing in a team environment. In-depth knowledge and hands-on experience with industry-standard physical design tools and methodologies, including synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification.

Teralynx series of switching products are key to Marvell cloud and AI market. IFCS SDK provides an interface for customer for Teralynx products. It is one of the critical component of the Teralynx products. With growing number of roadmap products and customers, we need more people and a leader to manage a team of developers. What You Can Expect Lead and manage a team of R&D engineers involved in the development of cloud Datacenter products of Marvell switching products. Responsible for the planning, execution, and delivery of software for Marvell switching products Contribute to the development of project goals and schedules. Demonstrate leadership and execute projects across a highly distributed engineering team. Work with various cross-functional groups such as Architect, other development teams, QA/Validation, System Test, Product Management, Product Documentation, Customer teams Collaborate and execute working with teams across various sites Responsible to mentor and train the team Manage the engineering resource allocation. Recruit, retain, and develop top engineering talent. Foster an inclusive, collaborative, and high-performance work environment. What Were Looking For The Software Engineering senior manager will lead the software development team to deliver innovative, high-quality software solutions that meet business objectives. We are looking for technology passionate leaders with focus on execution and quality to help innovate and develop highly scalable and distributed embedded network software. This role requires a strategic thinker with strong leadership skills and a deep technical background. The ideal candidate will be Bachelor s degree in Computer Science, Engineering, or a related field (Master s degree preferred). 10+ years of experience in software development, with at least 3 years in a management / leadership role. Proven track record of managing and delivering complex software projects. Strong knowledge of software development methodologies Excellent problem-solving, analytical, and decision-making skills. Strong communication and interpersonal skills. Experience in L2 switching/forwarding areas such as LAG, VLAN, xSTP, LLDP, Link OAM, ARP, VxLAN, DC fabric switching, etc. Experience in L3 unicast/multicast routing protocols such as RIP, OSPF, IGMP, BGP, ISIS, etc. Experience in embedded platform software for switching/routing products.

About Marvell . Your Team, Your Impact Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products. As part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out What You Can Expect Build and Lead a strong technical team of emulation experts to define emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium. Work with various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc. Work closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team. Define and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation Interface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience. Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification. Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Siemens including extensive experience in building complex SOC emulation models Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM) Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms. Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for implementing and validation DFT/Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Implementation of various DFT/DFX features, Scan/MBIST Insertion & Validation, ATPG , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 10+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN Insertion / ATPG / MBIST / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Strong fundamentals in Digital Circuit Design and Logic Design is required Knowledge on various DFT/Test solutions Understanding of DFT Flows and Methodologies and Experience with Siemens/Synopsys/Cadence Tool set (Tessent/DC, Spyglass, Tmax, VCS/Genus, Modus, NCSim ) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus