Principal Physical Design Engineer

Job Description

About Marvell . Your Team, Your Impact As member of the physical design team at Marvell you will have the opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design Signoff. Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff. Opportunity to work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more. What You Can Expect As a Principal Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 12+ years of experience running industry standard EDA tools for PnR signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1