400 Physical Verification Jobs

As a part of this role, you will be responsible for handling various bank-related tasks, managing vendor relationships, and conducting physical verifications of assets and stationary. Additionally, you will be required to vouch for and verify petty cash expenses, update G sheets, and verify company records. To excel in this position, you should possess a minimum of 2+ years of experience in the accounting field. A qualification such as CA Inter, B.Com, or M.Com would be preferred. Proficiency in G-sheets and Excel spreadsheets is essential for this role. If you meet these requirements and are looking for a challenging opportunity in the field of accounting, we encourage you to apply for this position.,

As a senior leader in the central physical design team at Marvell, you will shape the long-term vision for physical design capabilities and infrastructure in alignment with the company-wide technology strategy. You will lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS). Your role will involve providing strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs. Mentoring and developing engineering talent will be a key aspect of your responsibilities, fostering a culture of innovation, collaboration, and continuous improvement within the team. You will oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization. Driving cross-functional collaboration with design teams to influence design decisions and ensure successful project execution will also be part of your role. You will navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams. It will be your responsibility to drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality. Managing project schedules, resources, and risks to ensure alignment with business goals and customer requirements will also fall under your purview. Representing the physical design function in cross-org and executive-level discussions, contributing to long-term technology and product strategy will be expected. Collaborating with EDA vendors and internal CAD teams to evaluate and deploy new tools and technologies is also a crucial aspect of the role. We are looking for candidates with a Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field, along with 18+ years of progressive experience in back-end physical design and verification, including significant leadership roles. A proven track record in leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules is essential. Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges is required. Additionally, familiarity with AI/ML-driven optimization in physical design tools is considered a plus. Strong communication and collaboration skills, along with the ability to influence cross-functional teams and executive stakeholders, are also important qualities for this role. Proficiency in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness is expected. Marvell offers competitive compensation, great benefits, and a workstyle that promotes shared collaboration, transparency, and inclusivity. The company is dedicated to providing its employees with the tools and resources they need to succeed in meaningful work, grow, and develop within the organization. For more information on working at Marvell, visit our Careers page.,

Our client, Micron Technology, a global leader in memory and storage solutions, is seeking a Layout Design Engineer to join their HBM Team in Hyderabad, India. As a Layout Design Engineer at Micron Technology, you will play a crucial role in developing innovative technologies for applications such as artificial intelligence and high-performance computing solutions, specifically High Bandwidth Memory. In this position, you will collaborate with cross-functional teams across Micron's global footprint on multiple projects. Responsibilities include designing and developing critical analog, mixed-signal, and custom digital blocks, as well as providing full chip level integration support. You will be responsible for layout verification, quality checks, documentation, and ensuring on-time delivery of block-level layouts. Additionally, you will demonstrate leadership skills in project planning, scheduling, and execution, while also guiding junior team members and contributing to effective project management. The ideal candidate will have 8 to 15 years of experience in analog/custom layout design in advanced CMOS processes, expertise in tools such as Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS, and hands-on experience in creating layouts for critical blocks. A strong understanding of analog layout fundamentals, design constraints, and layout effects on circuits is required. Excellent communication and problem-solving skills, as well as experience in managing multiple layout projects, are also desired qualifications. Candidates should hold a BE or MTech in Electronic/VLSI Engineering. Micron Technology is known for its relentless focus on customer satisfaction, technological leadership, and operational excellence. If you are passionate about innovation and want to be part of a dynamic team shaping the future of memory and storage solutions, we encourage you to apply. To learn more about Micron Technology, Inc. and explore career opportunities, visit micron.com/careers. For assistance with the application process or accommodations, please contact hrsupport_india@micron.com. Micron Technology is committed to ethical practices and complies with all applicable labor laws and standards, including prohibiting the use of child labor.,

We are seeking enthusiastic individuals to join our team at Alphawave Semi, where we enable the next generation of digital technology by accelerating critical data communication. As a Physical Design Engineer in our IP Scaling (IPS) organization, you will play a key role in creating customized IP for our expanding customer base, delivering high-speed interconnect solutions for various industries such as High Performance Computing and Artificial Intelligence. Your responsibilities will include driving the backend process through the entire implementation flow, with a focus on floor-planning, power planning, low-power design, place & route optimization, clock tree synthesis, static timing verification, and physical verification. We are looking for someone with at least 5 years of Physical Design experience, a Bachelor's degree in Electrical or Computer Engineering (or equivalent), and advanced technology node experience. Attention to detail, strong collaboration and communication skills, analytical problem-solving abilities, consistency, and self-motivation are essential qualities we seek in our team members. At Alphawave Semi, we offer a flexible work environment that supports personal and professional growth. In addition, we provide a competitive compensation package, Restricted Stock Units (RSUs), opportunities for advanced education from premium institutes, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. We are committed to promoting diversity and inclusivity, welcoming applicants of all backgrounds and providing accommodations during the recruitment process. If you are passionate about driving innovation in the world of data communication and are eager to work with a dynamic team of talented individuals, we encourage you to apply for the Physical Design Engineer position at Alphawave Semi.,

Job Summary Physical verification engineer for SOC/blocks Key Responsibilities Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes. Address critical design and execution challenges associated with physical verification and sign-off. Have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Partner with PNR engineers to achieve sign-off at various stages of the design process. Qualifications and Skills Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2. Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs. Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. Capable of developing sign-off methodologies/flows and providing support to larger teams. Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset. Experience in floorplanning is a plus. Show more Show less

Job Overview As a part of in Arm&aposs Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is around the development of comprehensive implementation and analysis methodologies. Responsibilities Synthesis, Physical design and implementation of CPU cores, system interconnect and other ARM Designs. Analyze design timing, area and power to help improve the quality of ARM Design. Optimize design, flow and methodologies to achieve best in class PPAT working with various internal and external teams. Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results Required Skills And Experience Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification Strong Communication and Problem Solving Skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Experience working closely in top and block level Synthesis, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows. Proven programming and scripting skills eg. Tcl, Perl, Python, Make. Nice To Have Skills And Experience Knowledge around Arm based SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return At Arm, we are guided by our core beliefs that reflect our creative culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary. Accommodations at Arm At Arm, we want our people to Do Great Things. If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email [HIDDEN TEXT]. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Hybrid Working at Arm Arms hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done. Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email [HIDDEN TEXT] . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you. Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Show more Show less

Job Title : Material Handler Division Weir Minerals Location : Bangalore Onsite Purpose of Role: 1. To ensure accurate inventory management and operational efficiency through effective material handling, documentation, safety compliance, and continuous improvement practices in the stores function Why choose Weir: (Required) Be part of a global organization dedicated to building a better future: At Weir, the growing world depends on us. It depends on us constantly reinventing, quickly adapting and continually finding better, faster, more sustainable ways to access the resources it needs to thrive. And it depends on each of us doing the best work of our lives. It s a big challenge but it is exciting. An opportunity to g row your own way: Everything moves fast in the dynamic world of Weir. This creates opportunities for us to take on new challenges, explore new areas, learn, progress and excel. Best of all, there is no set path that our people must take. Instead, everyone is given the support and freedom to tailor-make their own career and do the best work of their lives. Feel empowered to be yourself and belong : Weir is a welcoming, inclusive place, where each individual s contribution is recognized and all employees are encouraged to innovate, collaborate and be themselves. We continually focus on people and their wellbeing. We believe in fairness and choose to be honest, transparent and authentic in everything we do. Key Responsibilities: 1.Taking care of Physical verification at the time of unloading. 2. Taking care of Material Put away once QC clearance. 3.Taking care of kitting as per Pick list. 4. Taking care of cycle count of material. 5. Take care of Safety, 6S and Win audits. 6. Accountability of inventory . 7.Taking care of Housekeeping. 8. Taking care of documentation of WIN S and SHE. Job Knowledge/Education and Qualifications: Diploma/ ITI/ Degree( 2 year of experience in auto/ heavy duty industries) For additional information about what it is like to work at Weir, please visit our Career Page and LinkedIn Life Page . #esco or #minerals (division) #LI-remote (working option) #LI-AB1 (Recruiter personal #)

Strong on Digital Design, SV, UVM. Hands-on experience in any of the DV protocols like PCIe, USB 3.0, DDR 3/4/5, AMBA, Ethernet (10G/100G), SATA, and MIPI (CSI/DSI), UFS, CXL Also Hiring PD, RTL, DFT Apply& Share resume to mansoor@hisoltech.com

As a Physical Design Engineer, you will be responsible for top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You should have experience working on 65nm or lower node designs with advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentoring to Physical Design Engineers and interface with front-end ASIC teams to resolve issues related to low power design techniques. Your responsibilities will also include timing closure on DDR2/DDR3/PCIE interfaces, ensuring excellent communication skills, and possessing a strong background in ASIC Physical Design encompassing Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. You should have extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools, expertise in scripting languages such as PERL, TCL, strong Physical Verification skill set, and proficiency in Static Timing Analysis in Primetime or Primetime-SI. In addition to technical responsibilities, you should have good written and oral communication skills, the ability to clearly document plans, and the capability to interface with different teams and prioritize work based on project needs. Qualifications: - Experience: 5 to 8 Years Location: - Hyderabad,

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understanding of the Physical Verification flow, with experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues primarily using the Calibre tool. Additionally, a deep understanding of ESD, latch-up, etc., is required. You will be responsible for owning and executing Physical Verification activities at the Top/Block level. Collaborating closely with the PD team to address their PV issues and suggest solutions is a key aspect of the role. Working with CAD team to refine existing flows/methodologies and resolve issues is also part of the job scope. Experience in IO, Bump planning, RDL routing Strategy, and developing/implementing timing and logic ECOs are considered advantageous. Knowledge of tools like Innovus/FC for DRC fixing, Python, PERL/TCL scripting, and the ability to plan, work independently, and coordinate with cross-functional teams are essential. Closing sign off DRC based on PNR markers is a plus. The ideal candidate should have experience with physical verification checks such as DRC, LVS, Antenna, ERC, PERC, ESD, etc. Experience with PnR tools like ICC/Innovus and understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV is required. A good overall understanding of the Custom IC design flow, layouts, and backend tool flow would be beneficial. Hands-on experience with tools like Innovus/Fusion Compiler, Tech lef is preferable. People management, floorplanning, power planning, and PDN experience are considered a big plus. The ability to script in TCL/PERL and familiarity with physical convergence in PnR tools are also advantageous. In return, we offer a competitive salary, performance-based bonuses, comprehensive benefits package including health insurance, retirement plans, and paid time off. Additionally, you will have opportunities for professional development and career growth in a collaborative and innovative work environment with state-of-the-art facilities.,

You should have a minimum of 6 years of experience in physical verification, with expertise in calibre tools for DRC, LVS, and antenna design. It is essential to possess good communication skills and experience in tape outs in 5nm and below technologies. The ability to collaborate effectively within a team and past experience working with block PD owners will be beneficial for this role. If you meet these qualifications and are interested in this opportunity, please send your CV to jyothi.malge@codersbrain.com. Your skillset should include proficiency in physical verification, design rule checking (DRC), and layout versus schematic (LVS).,

Eximietas is currently seeking Senior Physical Design Leads/Architects with at least 10+ years of experience to join their team in Visakhapatnam. Immediate joiners or those with a short notice period are preferred for this role. Qualifications: - A minimum of 10+ years of experience in Physical Design using mainstream P&R tools. - A Bachelor's or Master's Degree in Electronics, Electrical, Telecom, or VLSI Engineering. In this role, you will: - Work on designs using advanced nodes such as 10nm/7nm/5nm or lower, collaborating with various customers to meet performance, area, and power targets. - Develop flow and methodology for placement, clock-tree synthesis, and routing. - Provide training and technical support to customers. Key Technical and Professional Requirements: - Proficiency in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations. - Experience in hierarchical designs and Low Power implementation is advantageous. - Familiarity with Synthesis, collaborating with RTL and implementation designers for improved results. - Knowledge of Floor Plan design, encompassing placement of hard macros, padring, power grid, and custom analog routes. - Experience in Static Timing Analysis tasks such as constraints development, parasitic extractions, and sign-off requirements. - Understanding of Physical Verification processes including DRC, LVS, DFM, and chip finishing. If you are interested in this opportunity, please share your resume with maruthiprasad.e@eximietas.design. We look forward to receiving your applications!,

You are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognized for your ability to balance technical depth with practical implementation. Your expertise in I/O development, ESD (Electrostatic Discharge), and Latch-Up (LU) robustness sets you apart, and you are eager to build solutions that power the next generation of high-performance chips. You bring a strong foundation in FinFet, FDSOI, and BCD technologies, and you are excited by the prospect of owning projects end-to-end from conceptual design through to silicon qualification. Your approach is meticulous and data-driven, ensuring each design meets the highest standards of quality and reliability. You are comfortable working across cross-functional teams, collaborating with foundries, and integrating feedback from global stakeholders. Continuous learning excites you, and you embrace opportunities to mentor others, share knowledge, and contribute to a culture of technical excellence. You are motivated by the impact your designs have on real-world products and are committed to delivering robust, scalable, and innovative solutions for Synopsys worldwide customers. What You ll Be Doing: Designing and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes. Owning the full lifecycle of ESD structures from schematic design, simulation, and layout to silicon qualification and production release. Leading and executing I/O development, including I/O ring design, review, and optimization for performance and robustness. Developing and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements. Running ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity. Applying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality. Collaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions. The Impact You Will Have: Elevating the reliability and performance of Synopsys interface IPs, directly influencing the success of global semiconductor customers. Driving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry. Reducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions. Accelerating time-to-market for customer products through efficient and high-quality design practices. Fostering a culture of technical excellence and continuous improvement within the analog design team. Building strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects. What You ll Need: Proven experience in analog circuit design, with a focus on I/O development and ESD/LU robustness. Hands-on expertise with FinFet, FDSOI, and BCD process technologies from leading foundries. Strong background in ESD and Latch-Up qualification methodologies, including testchip development and validation. Proficiency in ESD simulation, ESD network construction, and use of industry-standard tools. Comprehensive understanding of PERC rules and practical experience with PERC verification tools. Experience working with cross-functional teams including foundry, design, and layout groups. Who You Are: An analytical thinker with excellent problem-solving skills and keen attention to detail. A collaborative team player who values diversity, inclusion, and open communication. A proactive learner who stays current with industry trends and emerging technologies. An effective communicator, able to translate complex technical information to diverse audiences. A results-driven individual who is adaptable, resilient, and comfortable with fast-paced, high-impact work. The Team You ll Be A Part Of: You ll join a passionate, multidisciplinary team of analog and mixed-signal engineers dedicated to advancing Synopsys interface IP portfolio. The team is focused on delivering robust, innovative, and high-quality solutions that meet the rigorous demands of a global customer base. Collaboration, continuous improvement, and technical mentorship are at the core of our culture, ensuring you ll have the support and opportunities needed to thrive and grow. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with a strong emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. The role involves working on cutting-edge technology nodes and applying advanced physical design techniques to push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Driving floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA Engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering with EDA tool vendors and internal CAD teams to develop and enhance automation flows and methodologies for improved design efficiency Making strategic trade-offs in design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design Expect strong self-motivation and time management skills Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found . Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors - Electronics Engineering 4-8 Years hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level. IR Signoff CPU/high performance cores Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP and other HMs Development of PG Grid spec for different HM Validating the PG Grid using Grid Resistance & Secondary PG Resistance Checks Validating the IR Drops using Static IR , Dynamic IR Vless & VCD Checks for validating Die & Pkg Components of IR Drops Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design Good knowledge on PD would is desirable. Python , Perl , TCL Skill Set Hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level. Good understanding on Power Integrity Signoff Checks. Proficient in scripting languages (Tcl and Perl). Familiarity with Innovus for RDL / Bump Planning/PG eco . Ability to communicate effectively with multiple global cross-functional teams. Tools Redhawk , Redhawk_SC and basic use case of Innovus/ Fusion Compiler Power Planning/Floor planning ,Physical Verification hands on experience is added advantage. LSF /compute optimization understanding. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Roles and Responsibilities Perform various electrical analyses at block and top levels, including static/dynamic IR, power/signal EM, and ESD Drive block and top-level electrical verification closure Develop power grid specs based on power/performance/area targets of different SOC blocks. Implement power grids in industry standard PnR tool environments. Work closely with the PI team to optimize the overall PDN performance. Work with CAD and tool vendors to develop and validate new flows and methodologies. Preferred qualifications BS/MS/PhD degree in Electrical Engineering; 4+ years of practical experience In-depth knowledge of EMIR tools such as Redhawk and Voltus Experience in developing and implementing power grid Good knowledge of system-level PDN and power integrity Practical experience with PnR implementation, verification, power analysis and STA Proficient in scripting languages (TCL/Perl/Python) Experience with industry standard EMIR tools such as Redhawk and Voltus Basic knowledge of the physical design flow and industry standard PnR tools Experience with scripting languages such as TCL, Perl and Python Ability to communicate effectively with cross-functional teams 4+ yrs exp in STA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems "which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl /Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor's/ Masters degree in Electrical /Electronic Engineering from reputed institution 2-10 years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

We are looking for a skilled SAP DRC Consultant with 19 years of experience to join our team at Forward Eye Technologies. The ideal candidate will have a strong background in SAP DRC and be able to work effectively in a fast-paced environment. Roles and Responsibility Collaborate with cross-functional teams to design and implement SAP DRC solutions. Provide technical expertise and support for SAP DRC projects. Develop and maintain documentation for SAP DRC implementations. Troubleshoot and resolve complex technical issues related to SAP DRC. Conduct training sessions for end-users on SAP DRC functionality. Work closely with stakeholders to understand business requirements and develop solutions. Job Requirements Strong knowledge of SAP DRC concepts, including data modeling and data validation. Experience working with various SAP modules, such as FI and CO. Excellent problem-solving skills and attention to detail. Ability to work independently and collaboratively as part of a team. Strong communication and interpersonal skills. Familiarity with industry-standard tools and technologies used in SAP DRC consulting.

KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 14years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 10years of experience in physical design role leading to an understanding of RTL to GDS development.

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. The ideal candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field. We are seeking PDN engineers with EMIR and PG planning expertise and a minimum of 4 years of experience. Responsibilities include IR signoff for CPU/high-performance cores, Signal EM & Power EM Signoff for Chip TOP level & Block level CPU/DSP, Development of PG Grid spec for different HM, and validating PG Grid and IR Drops. Additionally, working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations is crucial to enhance PDN Design. The desired skill set includes hands-on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level, proficiency in scripting languages like Tcl and Perl, and familiarity with tools such as Redhawk, Redhawk_SC, Innovus, and Fusion Compiler. The ability to communicate effectively with global cross-functional teams and experience in Power Planning/Floorplanning and Physical Verification is an added advantage. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. Abiding by all applicable policies and procedures, including security requirements, is expected from Qualcomm employees. Please note that our Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through this platform. Unsolicited submissions will not be considered. For more information about this role, please reach out to Qualcomm Careers directly.,

As part of this role, you will be responsible for ensuring accurate and timely accounting of inventory transactions in SAP. This includes conducting regular inventory reconciliations between physical stock and SAP records, as well as monitoring and analyzing inventory variances. In case of discrepancies, you will take corrective actions in coordination with the Regional Team. You will also play a key role in supporting monthly and annual inventory valuation and closing activities. This will involve coordinating and supporting physical stock counts, cycle counts, and audits. Additionally, you will be responsible for validating scrap, obsolete, and non-moving inventory provisions in line with company policy. Ensuring compliance with internal controls, Standard Operating Procedures (SOPs), and statutory guidelines related to inventory will be an essential part of your responsibilities. You will also liaise with internal and external auditors for inventory audits and queries. As part of driving continuous improvement, you will be expected to identify opportunities for process enhancements and automation in inventory accounting and controls. To excel in this role, you are required to have a B.Com / M.Com / CA Inter / MBA (Finance) qualification. Hands-on experience in SAP (MM & FI modules) is a must. A strong understanding of inventory accounting, valuation, and costing principles is essential. Prior experience in inventory management from a finance/accounting perspective, exposure to stock audit processes, and physical verification is preferred. Proficiency in Excel and ERP-based reporting is crucial for this role. You should also possess excellent coordination skills to work effectively with cross-functional teams and manage deadlines efficiently.,

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,

You should possess a B.Tech/M.Tech degree in Electronics and Communication Engineering with 8 to 20 years of experience in physical design of semiconductor chips. The role is based in Hyderabad and follows a general shift schedule with no work from home option. Your responsibilities will include top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks such as timing and functional ECOs, SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. You must have prior experience working on 65nm or lower node designs, implementing advanced low-power techniques like Voltage Islands, Power Gating, and substrate-bias. In this role, you will provide technical guidance and mentorship to physical design engineers, interface with front-end ASIC teams to resolve issues, and focus on low-power design techniques including Voltage Islands, Power Gating, and Substrate-bias. You should have expertise in timing closure on DDR2/DDR3/PCIE interfaces, excellent communication skills, and a strong background in ASIC Physical Design encompassing Floor planning, Place & Route, extraction, IR Drop Analysis, Timing, and Signal Integrity closure. Additionally, you should have extensive experience and detailed knowledge in physical design tools such as Cadence, Synopsys, or Magma, proficiency in scripting languages like PERL and TCL, and a strong skillset in Physical Verification. Familiarity with Static Timing Analysis using Primetime or Primetime-SI is required. Your written and oral communication skills should be excellent, with the ability to clearly document plans and effectively collaborate with cross-functional teams while prioritizing work based on project requirements.,

You are a Senior Physical Design Engineer with at least 6 years of experience, and your primary responsibility will be to lead the physical implementation of advanced semiconductor projects. Your role is crucial in shaping the silicon realization of cutting-edge designs, ensuring successful integration from RTL to tape-out. Your responsibilities include providing technical guidance and mentoring to physical design engineers, interfacing with front-end ASIC teams to resolve issues, and working on low power design techniques such as Voltage Islands, Power Gating, and Substrate-bias. You will also be responsible for timing closure on DDR2/DDR3/PCIE interfaces and have excellent communication skills. Your strong background in ASIC Physical Design, including floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, will be essential. You should have extensive experience and detailed knowledge in Cadence, Synopsys, or Magma physical Design Tools, as well as expertise in scripting languages like PERL and TCL. Additionally, you should have a strong Physical Verification skill set and experience in Static Timing Analysis using Primetime or Primetime-SI. In terms of required skills, you should be proficient in top-level floor planning, PG Planning, partitioning, placement, timing optimization, SI aware routing, and ECO tasks. Experience with 65nm or lower node designs with advanced low power techniques is necessary. Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification is also required. A Bachelors or Masters degree in electronics engineering or a related field is essential. Desired skills include familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, and Mentor Calibre, as well as knowledge of low power design techniques and implementation.,

As an Analog Layout Engineer at AISemiCon, you will play a critical role in the design and development of high-performance analog and mixed-signal integrated circuits (ICs). Your main responsibility will be to create layout designs for analog blocks and ensure their adherence to design rules, specifications, and performance targets. You will collaborate closely with cross-functional teams, including circuit designers, verification engineers, and process engineers, to achieve optimal layout implementation. We are seeking individuals with a strong passion for analog layout, deep expertise in IC design, and a keen eye for detail. The key responsibilities for this role include, but are not limited to: Requirements: Excellent work experience in Analog Layout design in advanced node processes Hands on experience in any or multiple critical blocks such as BGR, LDO, Charge pump, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of Analog Layout concepts (e.g. Matching, Electro- migration, Latch-up, Coupling, Cross-talk, IR-drop, Active and Passive parasitic devices etc. Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout. Work closely with the verification team to address layout-related issues and ensure design robustness. Follow design rules, guidelines, and best practices to ensure design manufacturability and yield. Collaborate with process engineers to understand process requirements and optimize layout designs accordingly. Conduct layout parasitic extraction and work with the simulation team to validate and optimize design performance. Participate in design reviews and contribute to overall design improvements. Stay updated with the latest advancements in analog layout techniques, process technologies, and industry standards. Qualifications: Bachelor s, Master s, or Ph.D. degree in Electrical Engineering or a related field. 7-8 Years of proven experience in analog layout design, with expertise in IC design methodologies and tools. Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc. Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area Proficiency in industry-standard layout tools, such as Cadence Virtuoso or Synopsys IC Compiler and verification tools in a Linux environment of Cadence EDA tools. Solid understanding of layout design principles, design rules, and process technologies. Familiarity with analog block-level and top-level layout techniques for performance optimization. Knowledge of layout parasitic extraction and simulation methodologies. Excellent attention to detail and problem-solving skills. Effective communication and collaboration skills to work in a cross-functional team environment. Applied Intelligence Semiconductors Private Limited (AISemiCon), an Innovative Product Enterprise is founded by seasoned semiconductor professionals, envisioned to deliver cutting edge products for the globe. At our company, we provide an innovative and collaborative workplace environment that empowers talented individuals to make a significant impact on the future of the semiconductor industry. We look forward to reviewing your application and discussing how you can contribute to our mission of advancing high-performance computing. Note: This job description provides a general overview of the responsibilities and requirements for the position and may be subject to change based on business needs. By using this form you agree with the storage and handling of your data by this website. *