602 Physical Verification Jobs

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node (180nm - 28nm) is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional

As a Custom Layout Engineer at our company, you will be responsible for acting as the focal point with customers and leading a team of 3-4 custom layout engineers. Your primary focus will be on analog layout, physical verification, and maintaining PDKs. Your expertise in critical layouts such as PLL, DLL, LNA, VGA, ADC, and LDO will be crucial for this role. Additionally, you should be able to quickly adapt to new technologies, tools, and flows. Key Responsibilities: - Work as a focal point with customers - Lead a team of 3-4 custom layout engineers - Handle analog layout, physical verification, and maintaining PDKs - Demonstrate expertise in critical layouts including PLL, DLL, LNA, VGA, ADC, and LDO - Adapt quickly to new technologies, tools, and flows - Mentor layout engineers - Collaborate with different teams and prioritize work based on project needs Qualifications Required: - BE/B.Tech /ME/M.Tech with 4-6 years of experience - Strong expertise in Custom Layout Standard Cells, I/O, or special analog designs - Experience in Pcell development, maintaining, and modifying PDKs - Proficiency in tools such as Virtuoso, Virtuoso-XL, Calibre, Hercules, and Assura - Expertise in SKILL Programming Language - Strong understanding of Analog Design - Good written and oral communication skills - Ability to clearly document plans In this role, you will play a critical part in the design and development process, ensuring the successful implementation of analog layouts and physical verification. Your ability to lead a team, collaborate with customers, and adapt to new technologies will be key to your success in this position.,

We are currently seeking a highly skilled Lead Physical Design Engineer to join our team on a temporary basis. As the Lead Physical Design Engineer, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex integrated circuits. Key Responsibilities: - Lead the physical design team in developing and implementing cutting-edge design methodologies - Collaborate with cross-functional teams to ensure project milestones are met - Perform floorplanning, placement, routing, and physical verification tasks - Optimize design for performance, power, and area - Troubleshoot and resolve design issues in a timely manner Qualifications: - Bachelors degree in Electrical Engineering or related field - Proven experience in physical design of complex integrated circuits - Proficiency in industry-standard EDA tools - Strong analytical and problem-solving skills - Excellent communication and teamwork abilities If you are a talented Physical Design Engineer looking to take on a leadership role in a dynamic environment, we encourage you to apply for this temporary position.

Job Specs : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations Preferred resources with valid regional work permit.

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Responsibilities: * Manage warehouse operations from transportation planning to stock inventory * Oversee loss prevention measures and physical verifications * Stock Maintenance for Production and FG etc. * Import and Export Materials and process. Annual bonus Provident fund Food allowance

We are At Synopsys, we pioneer innovations that shape our connected world Our technology powers the Era of Pervasive Intelligence, from self-driving cars to AI As leaders in EDA tools, chip design, verification, and IP integration, we enable the creation of high-performance silicon chips and software Join us to drive the future with continuous technological innovation, About You: You are a talented and dedicated Senior Layout Design Engineer specializing in analog and mixed-signal (A&MS) integrated circuits You excel in collaborative environments, working seamlessly with cross-functional teams to drive technological innovation Your meticulous attention to detail and unwavering commitment to quality are hallmarks of your work You are constantly striving to enhance layout design methodologies and best practices, utilizing your profound knowledge of semiconductor process technologies and industry-standard EDA tools Your exceptional problem-solving abilities, effective communication, and strong teamwork make you an indispensable asset, What Youll Be Doing: Develop and implement layout designs for A&MS integrated circuits, Optimize layouts using industry-standard EDA tools, Perform physical verification and design rule checks, Participate in Layout reviews and provide feedback, Collaborate with circuit designers on specifications and constraints, Enhance layout design methodologies and best practices, Stay updated with industry trends in A&MS layout design, The Impact You Will Have: Ensure high quality and performance of A&MS integrated circuits, Drive innovation with cutting-edge layout designs, Improve manufacturability and reliability through meticulous design, Contribute valuable feedback during design reviews, Foster continuous improvement in design methodologies, Mentor junior engineers by sharing your expertise, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show more Show less

As a curator / custodian at The House of MG, your role will involve managing the exquisite collection at Ahmedabad Trunk Heirloom Shop, Bookstore, Galleries & store. Your responsibilities will include custodianship of the mentioned areas, acquiring and authenticating artifacts, overseeing museum collections, curating and managing exhibitions, documentation & research, inventory and collection management, staff management, sales, audit & physical verification, restoration of damaged artifacts, and more. You will also be responsible for handling customers & VIP, VVIP, supervising new projects, vendor follow-up, pricing, and sales at the Trunk Gallery and Bookstore. Key Responsibilities: - Custodianship of Ahmedabad Trunk Heirloom Shop, Bookstore, Galleries & store - Acquiring and authenticating artifacts - Overseeing museum collections - Curating and managing exhibitions of Ahmedabad Trunk Products - Documentation & Research - Inventory management & Collection Management - Staff management - Sale, Audit & Physical verification regularly - Restoration of Damage artifacts - Vendor follow-up - Pricing of Trunk Gallery and Bookstore - Trunk Gallery and Bookstore Sales Qualifications Required: - At least 5 years of gallery / museum experience - Curatorial qualification The House of MG values proper documentation and management of all artifacts, ensuring their authenticity and proper display for retail. As a curator / custodian, you will play a crucial role in maintaining the integrity of the collection and providing a memorable experience for visitors.,

As an Officer/Sr. Officer in the Purchase Department, your role involves various responsibilities to ensure smooth operations. Your key responsibilities include: - Maintaining Purchase order Data Entry and Purchase order File - Ensuring accurate Good Received Data Entry and maintaining GRN File - Handling Material Issue Entry for Lab. Store and Clinic Store, and maintaining Indent File - Following up with parties for timely delivery of material - Receiving and verifying materials physically upon delivery - Issuing material from the Store Department - Entering Delivery challan for Data Entry of Good Receipt Note - Handing over Shortage Material Statement to Lab. Dept for release requisition - Conducting Physical Stock Checking monthly in Lab. Store and Clinic Store - Providing Stock Statement to Finance Dept for MIS - Passing Purchase Bills, obtaining approvals, and submitting them to the Finance Dept Basic Qualifications required for this role include being a graduate with 2 to 5 years of experience. If you are interested in this position, you can send your resume to dmirchandani@cliantha.com.,

Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes

Physical Deisgn Lead Location: Bangalore / Hyderabad / Pune Experience - 8+ YoE In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl. Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre). Well versed with timing constraints, STA and timing closure. Should have experience on Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Should have experience on programming in Tcl/Tk/Perl Well versed with timing constraints, STA and timing closure. Mandatory Skills: VLSI Physical Place and Route. Experience: 5-8 Years.

Role & responsibilities Store Sales Management 1 To Achieve weekly, Monthly & Yearly Volume Target Achievement 2 To Achieve Value Target & Achieve Suitable ASP for the month 3 Ensuring Focus Model Target Achievement & Higher sales of Flagship models. 4 Ensuring VBA are pitching Accessories at the time of sale to improve Addon selling. 5 To Ensure Store is in profit and achieving good Return of investments. 6 EOL handset liquidation on priority 7 To maintain stock level at store and make sure replenishment. 8 To take stock audit daily & weekly basis & manage 0 shrinkage. 9 To generate leads by doing society & company activation. Preferred candidate profile Store Management 1 To manage the store cost and profit 2 To work on company standard operating process 3 Ensuring store suitable stock & Daily, weekly stock count 4 Ensuring exclusive store good service for customers 5 Monthly Activity & Fans club Management 6 Customer management & service management 7 Customer lead generation & sales improvement 8 To Maintain Hygiene standard & VM Management as per company standards. 9 Frequent visit to franchise owner and discuss on Business plan monthly. Team Management 1 To manage VBA shifts leaves & daily timing 2 Morning & evening meeting with team 3 To improve VBA skills & communication & arrange monthly training 4 To ensure all VBA achieve their monthly target & increase star policy 5 Daily visit to storess & resolve issues of VBA in regards to sales & Store issue. 6 To insure proper grooming of VBA and hygiene level as per company standard.

Role & responsibilities : Review the Customer's Profile for Loan credit Worthiness. Visit in person for Verification. Analyze the credit worthiness and past track records of loans and repayments CIBIL Verification Maintain a detailed track report of clients Loan processing Attention to detail Preferred candidate profile 3-5 Yrs in Affordable housing segment HL/ LAP/ Mortgage Background (must) Ticket size of upto 1 Cr handling experience NBFC background only

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Required skills: Job Description: Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.

Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 8 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 10 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred : Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Job Requirements Job Title: Senior Engineer - Physical Design (PD) Job Type: Full-Time We are seeking a highly skilled and experienced Physical Design Lead in VLSI with a minimum of 3-7 years of experience to join our team. As the Lead Engineer in Physical Design, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex VLSI designs. esponsibilities: Lead the physical design (PD) team through complete ASIC/SoC implementation flow. Handle floorplanning, partitioning, placement, CTS (Clock Tree Synthesis), routing, and sign-off activities. Drive timing closure, power optimization, area optimization, and DRC/LVS clean designs. Collaborate with RTL, DFT, verification, and package teams to achieve project goals. Manage block-level and chip-level physical design, including hierarchical and flat methodologies. Perform static timing analysis (STA), power analysis, and signal integrity checks. Ensure physical verification, IR drop, and EM analysis closure. Guide junior engineers, review their work, and provide technical mentorship. Drive tool flow automation and efficiency improvements in PD. Interface with customers/stakeholders for updates, reviews, and sign-off. Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies. Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently. Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team. Education: B. E. /B. Tech or M. E. /M. Tech in Electronics, Electrical, or VLSI Design. Work Experience Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies. Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently. Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team.

Job Requirements Job Title: Lead Engineer - Physical Design (PD) Job Type: Full-Time We are seeking a highly skilled and experienced Physical Design Lead in VLSI with a minimum of 9 years of experience to join our team. As the Lead Engineer in Physical Design, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex VLSI designs. esponsibilities: Lead the physical design (PD) team through complete ASIC/SoC implementation flow. Handle floorplanning, partitioning, placement, CTS (Clock Tree Synthesis), routing, and sign-off activities.Drive timing closure, power optimization, area optimization, and DRC/LVS clean designs.Collaborate with RTL, DFT, verification, and package teams to achieve project goals. Manage block-level and chip-level physical design, including hierarchical and flat methodologies. Perform static timing analysis (STA), power analysis, and signal integrity checks.Ensure physical verification, IR drop, and EM analysis closure. Guide junior engineers, review their work, and provide technical mentorship.Drive tool flow automation and efficiency improvements in PD. Interface with customers/stakeholders for updates, reviews, and sign-off. Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently.Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team. Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design. Work Experience Required Skills: Strong hands-on expertise in physical design tools (Cadence Innovus / Synopsys ICC2 / Mentor). Solid understanding of ASIC design flow and foundry process nodes (7nm/5nm/14nm or relevant). Deep knowledge of STA, power analysis, IR/EM, and physical verification methodologies.Good experience in ECO (Engineering Change Order) flows. Familiarity with scripting languages (TCL, Perl, Python) for automation. Proven experience handling full chip/block-level PD independently.Strong problem-solving and debugging skills. Good communication and leadership abilities to lead a PD team.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is seeking passionate, highly motivated, and creative design engineers to be part of a team working on industry-leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What you'll be doing: In this position, you will expected to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification. Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design related issues. Constantly look for improvement in RTL2GDS flow to improve PPA. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. What we need to see: BE/BTECH/MTECH, or equivalent experience. 1+ years of experience in Physical Design. Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure. Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation. Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA and timing closure. Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Ability to multi-task and flexibility to work in global environment. Good communication skills and strong motivation, Strong analytical & Problem solving skills. Proficiency using Perl, Tcl, Make scripting is preferred. Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family NVIDIA is committed to encouraging a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 8+ years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Additional Job Description Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing ]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 12+ years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers onfloor-planning expertise at both block and top levelsfor industry-leadingCPU core designs, with a strong emphasis on scalability and achieving aggressivePower, Performance, and Area (PPA)targets. The role involves working oncutting-edge technology nodesand applyingadvanced physical design techniquesto push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Drivingfloorplan architecture and optimizationin collaboration with PD/RTL teams to maximize PPA Engaging incross-functional collaborationwith Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering withEDA tool vendorsand internal CAD teams to develop and enhanceautomation flows and methodologiesfor improved design efficiency Makingstrategic trade-offsin design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design less than 10nm Expect strong self-motivation and time management skills