Principal Engineer - Physical Design

Job Description

This position is with ASIC design physical implementation (PD) team part of Central Engineering business unit at Marvell, Bangalore. This team as part of global Implementation team plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s. We are looking for individuals with the domain of physical design having Block /Subsystem level implementation experience on hierarchical designs using industry standard tools. What You Can Expect Work with a global team on the physical design of complex chips at Block/Partition/Full-Chip level. You will also play a critical role in refining the methodology to enable an efficient and robust design process working closely with the methodology team. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on a given hierarchical design at block/partition/full-chip level. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Collaboration with the frontend team will be crucial to ensure successful tapeouts. Additionally, your involvement with the global timing team will include debugging and resolving any block/partition level timing issues encountered at the Chip level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 15+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs. In your coursework, you must have completed a course in digital electronics, CMOS design and projects that involved circuit design & analysis. Good understanding of standard RTL to GDS flows and methodology, experience in designing ICs at advanced technology nodes (e. g. , 7nm, 5nm, or below) is highly desirable. Working knowledge on any of the scripting in languages such as Perl, tcl, AWK and Python. Knowledge of Verilog/VHDL basics is an added advantage. Good communication skills and self-discipline contributing in a team environment. In-depth knowledge and hands-on experience with industry-standard physical design tools and methodologies, including synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification.