Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional SMTS Verification Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer Responsibilities RESPONSIBILITIES Develop test plans, tests and verification infrastructure for complex IPs/sub-system/SOCs Create verification environment using UVM methodology Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure Work with architects, designers and post-silicon teams Qualifications Bachelors / Masters degree in Electronics/Electrical Engineering 5 to 7 year of verification experience exposure in HVL based verification with expertise in SV & OVM Exposure in High Speed IO verification (UFS/PCIE/ XUSB) Good understanding of memory technology and memory sub-system Should have knowledge on all aspects of verification components & verification closure Should have flair for documentation, defining/improving methodology and achieving productivity improvement Ability to provide technical guidance & resolving technical conflicts desired Ability to communicate technical and project issues to business and technical senior management MUST have very good verbal and written communication skills About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow s systems. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ .

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead MTS Physical Design Engineer to join our MIC Design IDC team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip s for full chip timing analysis. we'll aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 8 years should be related to STA/Synthesis . Must have Involved in high Speed design tape-outs and constraint development across modes. Must have detailed knowledge of Constraints , Signoff closure methodology for STA and RTL2GDS flow is desired Experience in Tcl/Tk, PERL is a Plus.

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Sr. Principal Engineer with signal integrity and package design experience to join our Memory Interface Chips BU s engineering team in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As an SPE Signal Integrity Engineer, you will be reporting to the VP of Engineering and is a Full Time position. In this highly visible role, you will work within our SI/PI team to work on modeling, analysis, and simulations of signal integrity (SI) and power integrity (PI) in the very challenging DDR field with speed up to 12800+ MT/s. Responsibilities Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores Work with our customers to do collaboration to find the optimum SI/PI solution Help the team during debug and bring up in lab if needed Qualifications Solid background in SI/PI and package design to provide technical leadership to the team Strong interpersonal skill to keep the team motivated and focused MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5 Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required Solid theoretical background and understanding in EM and transmission line theory is a must Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc. Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations Proficient with simulations using Spice and ADS Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus Basic knowledge of circuits used in high-speed link design is preferred. Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams. Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player About Rambus With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for todays most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. The US- San Jose salary range for this full-time position is $141,500 to $281,000. Our salary ranges are determined by role, level and location. The successful candidate s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/ . #LI-GL1