Senior Staff Manager - DFT

Job Description

Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position is for a Techno-Managerial role who will be responsible for Managing a team of skilled DFT-engineers who work on implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs. The management responsibilities include but not limited to handling career-development, mentoring and monitoring project execution. As a senior technical leader, the role also involves driving end to end DFT-execution on SoCs and Subsystems, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Management experience - Must have directly managed small sized teams , members HandsOn Working experience in various stages of DFT-Execution SCAN-Insertion / MBIST / ATPG / Validation / STA / IP-DFX / Post-Silicon Bringup/Debug Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus, Modus, NCSim / DC, Tessent, Spyglass/Tmax) Prior experience in Custom-ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus