PMTS Silicon Design Engineer Advanced Micro Devices, Inc

15.0 - 19.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: At AMD, you will be working as an ASIC Verification Engineer. Your role will involve driving strategies and successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs. You will be contributing to the mission of building great products that accelerate next-generation computing experiences, from AI and data centers to PCs, gaming, and embedded systems. Grounded in a culture of innovation and collaboration, you will be part of a team that believes in pushing the limits of innovation to solve the world's most important challenges. Key Responsibilities: - Technically lead a team and work with cross-functional teams, pla...

Posted 1 week ago

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Technical Lead ASIC Verification Engineer Advanced Micro Devices, Inc

15.0 - 19.0 years

0 Lacs

hyderabad, telangana

On-site

As an ASIC Verification Engineer at AMD, your role is crucial in driving strategies and successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs. Your responsibilities include: - Demonstrating a proven track record in technically leading a team and collaborating with cross-functional teams - Planning inter-locks with dependent teams and preempting risks with mitigation plans - Developing UVM/OVM and/or Verilog, System Verilog test benches - Utilizing simulation tools/debug environments like Synopsys VCS, Cadence IES for verifying high-performance IPs and/or SOC designs - Implementing state-of-the-art verification techniques, in...

Posted 1 month ago

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Technical Lead ASIC Verification Engineer AMD

15.0 - 19.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: You will be joining AMD as an ASIC Verification Engineer. Your main responsibility will be to drive strategies and lead successful verification execution on Block level and System level verification of high-performance IPs and/or SOC designs. Key Responsibilities: - Lead a team and collaborate with cross-functional teams to plan inter-locks with dependent teams, pre-empt risks, and have mitigation plans in place. - Develop UVM/OVM and/or Verilog, System Verilog test benches and utilize simulation tools/debug environments like Synopsys VCS, Cadence IES for verifying high-performance IPs and/or SOC designs. - Implement state-of-the-art verification techniques including assertion...

Posted 2 months ago

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