Vlsi Design And Verification Engineer | Semiconductor Design Engineer Acesoft Labs

2.0 - 7.0 years

8 - 18 Lacs

hyderabad

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Role & responsibilities Description : Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience in Designing & Verification Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects ...

Posted 1 week ago

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Semiconductor Design Engineer Acesoft Labs

3.0 - 7.0 years

0 - 1 Lacs

hyderabad, bengaluru

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Role & responsibilities Description: Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience • Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. • Provide verification support to design projects by simulating, analyzing ...

Posted 3 weeks ago

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DV Engineer -GLS Honeybee Tech Solutions

5.0 - 9.0 years

10 - 20 Lacs

Bengaluru

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Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contri...

Posted 2 months ago

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Design Verification Engineer | UVM SystemVerilog Coventine Digital

3.0 - 8.0 years

6 - 14 Lacs

Bengaluru

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We are actively hiring multiple Design Verification (DV) Engineers for Bangalore (hybrid model). If youre looking for a new challenge and can join quickly, youll be among our top-priority candidates! Open Positions : 1. DV Engineer GLS / UVM / SystemVerilog / CDC Experience : 3–8 years Skills : Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification 2. DV Engineer – PCIe / DDR / UVM / SV Experience : 4–18 years Skills : Protocol-level verification, PCIe or DDR, UVM, SystemVerilog 3. DV Engineer – UVM / SystemVerilog Experience : 5–10 years Skills : Testbench architecture, functional verification, scalable UVM environments

Posted 2 months ago

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