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Together, we advance your career.
Engineering Manager - IP Design Verification
Role Overview
As an
Engineering Manager
for the
Data Fabric Design Verification team
, you will lead a team of skilled verification engineers in developing and executing verification strategies for AMD's high-performance Infinity Fabric IP. You will be responsible for team leadership, project delivery, technical guidance, and cross-functional coordination to ensure first-pass silicon success for next-generation AMD CPUs, GPUs, and APUs.
Key Responsibilities
- Lead and manage a team of design verification engineers, providing technical direction, mentorship, and performance feedback.
- Define and drive verification strategy for Data Fabric IP, ensuring alignment with architectural goals, schedule, and quality targets.
- Oversee test plan creation, review, and execution for block- and system-level verification.
- Ensure functional and code coverage closure, and track verification quality metrics for all deliverables.
- Collaborate with design, architecture, and performance engineering teams to resolve complex technical issues and optimize verification approaches.
- Prioritize and allocate resources across multiple verification tasks and projects, balancing execution speed with quality.
- Champion verification methodology improvements, automation initiatives, and best practices across the team.
- Support post-silicon debug efforts, helping to recreate and root-cause lab or customer-found issues.
- Represent the verification team in project reviews, planning meetings, and executive updates.
Required Skills & Experience
- Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs.
- Strong expertise in SystemVerilog, UVM, and coverage-driven verification methodologies.
- Deep understanding of computer architecture, digital logic design, and high-speed interconnect/fabric protocols.
- Hands-on experience with EDA tools (Synopsys VCS, Cadence Xcelium, Mentor Questa).
- Excellent debugging and problem-solving skills for complex, multi-clock domain designs.
- Scripting proficiency in Python, Perl, or similar for automation and regression management.
- Strong people management and communication skills to lead geographically distributed teams.
Preferred Background
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of experience in ASIC/SoC verification, with at least 3+ years in a management or technical leadership role.
- Experience working with multi-site, cross-functional teams in a fast-paced semiconductor environment.
- Familiarity with formal verification and emulation/prototyping flows is a plus.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
