17 Functional Coverage Jobs

Job description In this role, you will be creating UVM testbenches for a SoC and IP, as well as tests, regressions, and functional coverage to achieve zero bug escapes. You will interface with the designers to develop the test plans, and from that develop testcases and coverage to thoroughly verify the RTL. Your regressions will grow to cover the full functionality of the design relative to the architectural simulator and will include corner case testing for the more challenging cases. Your test and coverage reviews will ensure key coverage. ESSENTIAL DUTIES AND RESPONSIBILITIES: Create UVM testbenches, tests, and constraints to ensure design correctness Design, develop, and maintain modular and reusable UVM testbenches for blocks Collaborate with colleagues to develop test plans Create randomized tests, adding constraints and directed tests to fully cover functionality Confirm test completeness through code and functional coverage Review testbenches, tests, and coverage with designers, architects, and SW engineers Integrate tests and coverage within full environment Write C based BareMetal code for SoC level verification Relevant experience of 3-10 years Show more Show less

As a Lead Verification Engineer with over 7 years of experience, you will be an integral part of a geographically distributed verification team working on next-generation ASIC and FPGAs. Your responsibilities will include developing testplans, implementing testbenches, creating testcases, and ensuring functional coverage closure. Additionally, you will handle regression testing, contribute to verification infrastructure development, and develop both directed and random verification tests. In this role, you will be expected to debug test failures, identify root causes, and collaborate with RTL and firmware engineers to resolve design defects and test issues. You will also review functional and code coverage metrics, modify or add tests, and constrain random tests to meet coverage requirements. Furthermore, you will collaborate closely with design, software, and architecture teams to verify the design under test. The preferred experience for this role includes proficiency in IP-level FPGA and ASIC verification, knowledge of protocols such as PCIe, CXL, or other IO protocols, and proficiency in Verilog/SystemVerilog and scripting languages like Perl or Python. Hands-on experience with SystemVerilog and UVM is mandatory, along with experience in developing UVM-based verification testbenches, processes, and flows. A solid understanding of design flow, verification methodology, and general computational logic design and verification is also essential. About the Company: ACL Digital, a leader in digital engineering and transformation and part of the ALTEN Group, empowers organizations to thrive in an AI-first world. With expertise spanning the entire technology stack and seamlessly integrating AI and data-driven solutions from Chip to cloud, ACL Digital offers a strategic advantage in navigating the complexities of digital transformation. Join us at ACL Digital and be a part of shaping the future as our trusted partner.,

THE PERSON: You will have strong analytical/problem solving skills, high attention to detail, and motivation toindependently drive tasks to completion. You will also have professional interpersonal and communication skills.If this sounds like a role you are interested in, we welcome you to apply! KEY RESPONSIBILITIES: Development and verification of embedded firmware for SOC secure boot and embedded microprocessor driven hardware acceleration services for cryptography, decompression and large scale DMA functions. Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench. Hardware/Firmware co-verification in FPGA hardware prototype platform. Develop and maintain subsystem verification architecture, testbench, test methodology for Embedded CPU and subcomponent IPs with AXI/AHB busses and HW accelerators such as Cryptography, Data Compression, DMA, etc Participate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance model Create abstracted FW and HW performance models Develop critical target code to collect IP performance key parameters Explore subsystem architecture performance trade-off for FW and HW optimization Develop and execute subsystem and block level test plans Develop FW/HW co-verification methodology Develop UVC and System Response models Develop and debug UVM and C-DPI test cases with integrated FW Improve verification metrics Further develop subsystem and block level testbenches using UVM randomized test methodology and C-DPI directed test methodology. Develop and maintain subsystem level integration scripts Develop and maintain subsystem testbench build and test run scripts Drive to verification metrics closure Interface with SoC integration and SoC DV teams Define and develop IP level DV API to support SoC level DV effort Develop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs. Support SoC level IP emulation, silicon bring-up and debugging effort PREFERRED EXPERIENCE: ASIC FW and HW design and verification experience Proficient in C, C++, Assembly, Verilog, System Verilog, and several scripting languages (Make, Perl, Python, etc) Excellent knowledge about UVM methodology and C-DPI methodology Excellent knowledge about standard bus/interface protocols (ie AXI, AHB, AMBA) Excellent experience with firmware design on commercial microprocessors Excellent experience with microprocessor tool chain, compiler, assembler, debugger Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc ACADEMIC CREDENTIALS: Major in Electrical or Computer Engineering. B.Eng or masters or PhD Degree preferred.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in micro-architecture and design of IPs and subsystems. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or Perl). Experience in SoC designs and integration flows. Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performance and low power design techniques. Responsibilities Own implementation of IPs and subsystems. Work with Architecture and Design Leads to understand micro-architecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance, and Area improvements for the domains.

As a Semiconductor Design Engineer 2 with 3-5 years of experience, based in Hyderabad, you will be responsible for fast spice (Prime sim/Fine sim/spectre) based verification. Your role will involve guiding and setting the direction for the verification effort within your areas of expertise in any project that the team undertakes. You should possess strong circuit understanding, block-level circuit simulation, and analysis capability. Additionally, you are expected to analyze the test modes, have basic DFT understanding, and provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Your responsibilities will include developing test cases/stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. You will participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Collaboration with international colleagues on developing new verification flows to address the challenges in DRAM and emerging memory design is also a crucial aspect of this role. Furthermore, you will be involved in the development and maintenance of test benches and test vectors using simulation tools. Running regressions for coverage analysis and improvements will be part of your routine tasks. Your contribution to the team will be vital in ensuring the successful verification of semiconductor designs and in driving innovation in the field of DRAM and emerging memory products.,

Job Description: We are looking for an experienced SoC DV Lead with a strong background in SoC verification and hands-on experience in writing C test cases for SoC-level DV. Key Responsibilities: Lead SoC DV activities from planning to closure Develop and debug C-based test cases for system-level verification Work closely with design, architecture, and firmware teams Perform coverage analysis and ensure comprehensive validation Guide and mentor junior DV engineers Key Skills: SoC-level design verification C programming for test development Debugging and problem-solving Exposure to UVM/SystemVerilog (preferred) Strong understanding of SoC architecture

As a Verification Engineer, you will be responsible for utilizing your 2+ years of experience in ASIC/FPGA verification to develop test plans and verification strategies that thoroughly and effectively validate requirements and specifications. Your expertise in developing SV + UVM based verification environment components, such as agents/UVCs, scoreboards, predictors/reference models, and creating tests using constrained random based test sequences will be essential for success in this role. Your role will also involve implementing functional coverage, identifying and resolving coverage gaps, and writing tests to ensure comprehensive verification. Additionally, you will have the opportunity to contribute to code coverage activities and enhance the overall verification process. To excel in this position, you should possess strong problem-solving skills and be capable of working both independently and collaboratively as part of a team. Your familiarity with scripting languages like GNU make, Perl, and Python will be advantageous, along with any experience in FPGA verification compliance to DO-254 standards. Exposure to verifying DSP blocks, such as filters, adders, multipliers, and limiters using fixed-point operations, will further enhance your contributions to the verification process. Overall, your ability to communicate effectively, both verbally and in writing, will be crucial in ensuring successful collaboration and project outcomes. If you are a trained fresher with a passion for verification engineering, you are also encouraged to apply and contribute your skills to our dynamic team.,

This is a verification-focused individual contributor's role within the DesignWare IP Verification R&D team at our Bangalore Design Center, India. As a part of this team, you will be responsible for implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores and executing Verification tasks for the IP cores. You will collaborate closely with the RTL design team and work alongside a global team of expert Verification Engineers. The domains you will be working on include USB, PCI Express, Ethernet, and AMBA. Your responsibilities in this role will encompass a variety of tasks such as Test planning, Test environment coding at both unit and system levels, Test case coding and debugging, FC coding and analysis, and achieving quality metric goals and regression management. To be considered for this position, you should have a BS/BE in EE with 7+ years of relevant experience or an MS with 6+ years of relevant experience in IP cores verification and/or SOC verification. You should possess experience in developing HVL-based test environments, creating and implementing test plans, and extracting verification metrics like functional coverage. Additionally, you must have proficiency in HVL coding for Verification and hands-on experience with industry-standard simulators such as VCS, NC, MTI, along with relevant debugging tools. Exposure to verification methodologies like UVM/VMM/OVM is essential, and familiarity with HDLs such as Verilog and scripting languages like Perl is highly desired. A basic understanding of functional & code coverage, exposure to IP design and verification processes including VIP development, and good written and oral communication skills are crucial for this role. You should also be able to demonstrate strong analysis, debugging, problem-solving skills, and be self-driven. Join our Silicon IP business, where we focus on integrating more capabilities into an SoC faster. Synopsys offers the world's broadest portfolio of silicon IP, pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors. We aim to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and bring differentiated products to market quickly with reduced risk. At Synopsys, we are at the forefront of innovations that reshape the way we live and work, including self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. Our advanced technologies for chip design and software security power these breakthroughs. If you are passionate about innovation, we look forward to meeting you.,

Description We are seeking a skilled Verification Engineer to join our team in India. The ideal candidate will have a strong background in digital design verification and will be responsible for ensuring the quality and reliability of our products through rigorous testing and analysis. Responsibilities Develop and implement verification plans and test cases for digital designs. Perform functional and performance verification using simulation and formal verification techniques. Collaborate with design engineers to understand specifications and requirements. Debug and analyze issues found during verification, providing feedback to design teams. Generate reports and documentation for verification activities and results. Skills and Qualifications 3-6 years of experience in GLS verification engineering or related field. Strong knowledge of digital design concepts and verification methodologies. Proficiency in SystemVerilog and UVM (Universal Verification Methodology). Experience with simulation tools like ModelSim, Questa, or similar. Familiarity with scripting languages such as Perl, Python, or TCL for automation tasks. Understanding of RTL design and coding practices. Ability to work collaboratively in a team environment and communicate effectively.

Job Description Summary Oracle HCM Tech (Integrations, Data Conversion , Reports, Fast Formulas , OIC(Optional)) + Functional Coverage Job Description Functional knowledge of Compensation and Equity area in Oracle is plus -HCM Techno-Functional Engineers / Integration Engineers with core expertise in HCM extract , HCM API integration , HDL imports . Added expertise in Mulesoft would be a highly desirable but not mandatory. Oracle HCM Tech (Integrations, Data Conversion , Reports, Fast Formulas, OIC(Optional)) + Functional Coverage. Hands-on expertise with Oracle HCM tools such as OTBI, BI Publisher, and HDL/SDL. Optional experience with Oracle Integration Cloud (OIC) is a strong advantage. Strong problem-solving skills with the ability to work independently and collaboratively in a team. Excellent communication and documentation skills.

Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies Developing and tracking of Verification plans Develop verification environments from scratch Create VIP Integration of VIP (Verification-IP) Measure and analyze regression results Continuous improvement of verification methods/tools/flows/processes together with EDA partners Requirement: 5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM. Sound knowledge of constrained random verification, UVM/OVM Sound knowledge in System Verilog. Experience of developing functional coverage code, coverage analysis. Experience of developing verification environments from scratch is desirable. Good hands on experience with cadence/Synopsys/Mentor tools. Exposure to configuration management, bug tracking tool etc. Knowledge of scripting language, Perl TCL etc. Good experience with AMBA protocols Working knowledgeon ARM processor-based subsystem/SoC verification Formal verification experience is a desirable but not must. Must have been a part of one or more ASIC/SoC tape outs. Knowledge of VHDL/VERILOG. SPECMAN knowledge is a desirable but not must.

Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers, VIP team to accomplish tasks Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Work with peers to improve methodologies and improve execution efficiency Adhere to quality standards and good test and verification practices Work as a lead, mentor junior engineers, and help them in debugging complex problems Support customer issues, by their reproduction and analysis Should be able to multitask between different activities Key Qualifications: Proven desire to learn and explore new state-of-the-art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM Good organization and communication skills Be a solution provider 8+ years of relevant experience

Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers, VIP team to accomplish tasks Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Work with peers to improve methodologies and improve execution efficiency Adhere to quality standards and good test and verification practices Work as a lead, mentor junior engineers, and help them in debugging complex problems Support customer issues, by their reproduction and analysis Should be able to multitask between different activities Key Qualifications: Proven desire to learn and explore new state-of-the-art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM Good organization and communication skills Be a solution provider 8+ years of relevant experience

Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc ) Generate verification test plan, verification environment documentation and test environment usage documentation Define, develop, and verify complex UVM verification environments Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers, VIP team to accomplish tasks Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Work with peers to improve methodologies and improve execution efficiency Adhere to quality standards and good test and verification practices Work as a lead, mentor junior engineers, and help them in debugging complex problems Support customer issues, by their reproduction and analysis Should be able to multitask between different activities Key Qualifications: Proven desire to learn and explore new state-of-the-art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM Good organization and communication skills Be a solution provider 8+ years of relevant experience

Specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores. Perform verification tasks for IP cores, working closely with RTL designers. Drive ownership of critical areas of verification along with a team of talented verification engineers. Develop and implement advanced test plans and test environments at both unit and system levels. Code and debug test cases, implementing complex checkers and assertions. Extract and review functional coverage (FC) and code coverage metrics, ensuring quality metric goals are met. Manage regressions and contribute to the continuous improvement of verification strategies and test environments. The Impact You Will Have: Enhance the quality and efficiency of our verification processes, ensuring robust and reliable IP cores. Contribute to the development of cutting-edge technologies that power the Era of Smart Everything. Enable the creation of high-performance silicon chips and software content, driving innovation in various industries. Collaborate with a global team of experienced verification engineers, fostering a culture of knowledge sharing and continuous learning. Play a key role in the success of Synopsys DesignWare IP Verification R&D team, contributing to our leadership in chip design and software security. What You'll Need: BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience. Proven experience in developing HVL (System Verilog/UVM) based test environments. Expertise in developing and implementing test plans, checkers, and assertions. Proficiency in extracting verification metrics such as functional coverage and code coverage. Experience with memory interface protocols (DDR, LPDDR) and IP design and verification processes.

What You'll Be Doing: Developing and reviewing verification plans for SERDES/PHY/Controller IPs. Creating and maintaining verification environments, with a preference for UVM. Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure. Delivering high-quality RTL and simulation models to customers. Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems. Supporting customers with IP integration, silicon bring-up, and debugging issues. Demonstrating Testchip+FPGA system demos to customers and at conferences. The Impact You Will Have: Ensuring the compliance and functionality of our interface IPs with industry protocols. Enhancing the quality and reliability of our silicon solutions for customers. Facilitating smooth customer adoption and integration of our IPs. Contributing to successful silicon bring-up and debugging efforts. Showcasing our technological advancements at industry events. Driving innovation and excellence in digital design and verification processes. What You'll Need: Expertise in one or more interface protocols (e.g., USB, PCIe, Ethernet, JESD204B). Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). Experience with SERDES/PHY/Controller IP specification and compliance validation. Strong background in developing and reviewing verification plans and environments. Ability to deliver high-quality RTL and simulation models to customers.

Creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chip-to-chip, die-to-die, coherent, and non-coherent design topologies. Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Arm AMBA AXI/ACE, CHI; CCIX or CXL Cache. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification.