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5.0 - 10.0 years
6 - 12 Lacs
pune
Work from Office
Responsibilities: Must have experience in Verilog, System Verilog, UVM, VLSI, SPECMAN e, Unix, Linux, Python
Posted 3 days ago
10.0 - 12.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Are you ready to be at the forefront of innovation and efficiency As a Principal Engineer Functional Verification, you will ensure the most efficient development of Infineon products with right quality, delivered with first time success. You will play a crucial role in Infineon's value creation chain, contributing directly to product development and focusing on efficient execution, maintenance, and continuous improvement. Job Description As a Principal Engineer Functional Verification, you will take on a pivotal role in defining and implementing advanced verification concepts for complex SoCs. You will be responsible for designing testbench architectures, coordinating comprehensive verificat...
Posted 2 weeks ago
2.0 - 6.0 years
0 Lacs
karnataka
On-site
As a Verification Engineer, you will be responsible for designing and developing test benches using HVLs like System Verilog, Specman, etc. Your deep expertise in Verification Methodologies such as OVM, UVM, VMM will be crucial in creating verification environments and test plans. Additionally, having domain expertise in Networking protocols, Interface protocols like PCIe, USB, SATA, or SoC Verification will be a plus. Your familiarity with scripting languages and good communication skills will enable you to excel in this role. If you have a BE/B.Tech/ME/M.Tech or equivalent in ECE/EEE, this position is perfect for you. - Design and develop test benches using HVLs like System Verilog, Specma...
Posted 2 weeks ago
8.0 - 10.0 years
0 Lacs
bengaluru, karnataka, india
On-site
ACL Digital Hiring for the below requirement Designation: DV engineers Experience: 8-10+ years Location: Bangalore Job Description: 1. Hands-on experiences on SV/UVM/Specman 2. Familiarity with formal-based verification 3. Running regression and debugging failures independently 4. Experience in functional and code coverages 5. Independently handling sub-module-level verification 6. Clear written/verbal communication skills. 7. Familiarity with PIPE i/f or Ethernet is a must; it's good to have basic knowledge of PCIe and/or high-speed Ethernet. 8. Familiarity in mixed signal IP (SerDes, DDR) verification will be a plus.
Posted 3 weeks ago
4.0 - 8.0 years
14 - 54 Lacs
pune
Work from Office
Title: Sr. Design Verification Engineer / Lead Verification Engineer Location: Offshore onsite (Pune, Ahmedabad) Duration: Full-Time MIO: Skype + F2F Looking an experienced Design Verification Engineer to join our growing team. Health insurance Annual bonus Provident fund
Posted 4 weeks ago
8.0 - 10.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in Design Verification (DV). Experience in developing and deploying state of the art verification methodologies. Experience in any one of the hardware description languages (HDL) (e.g. Verilog/SystemVerilog). Experience with Python for scripting, automation, and data analysis in a verification context. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience with AI/ML frameworks and tools such ...
Posted 1 month ago
5.0 - 9.0 years
0 Lacs
bengaluru, karnataka, india
On-site
Position : Senior Design Verification (DV) Engineer Experience : 5-9 years Location : Bangalore Work Mode : Work from office Job Type : Full-time Job Summary We are seeking a highly skilled and experienced Senior Design Verification (DV) Engineer with 5-9 years of experience to join our team in Bangalore. The ideal candidate will be a hands-on expert in SystemVerilog and UVM methodologies, responsible for implementing robust verification environments, analyzing test coverage, and debugging complex logic issues. This role is crucial for ensuring the functional correctness and quality of our chip designs through rigorous verification and testing. Key Responsibilities Verification Environment D...
Posted 1 month ago
8.0 - 15.0 years
0 Lacs
karnataka
On-site
The culture at the organization is defined by its people. There is an emphasis on fostering a culture where individuals are passionate about technology solutions that have a meaningful impact on businesses. It is also ensured that employees are encouraged to pursue their personal passions. Being a part of the team provides you with a deep insight into a variety of industries and cutting-edge technologies, enabling the creation of futuristic and impactful solutions. Moreover, the experience gained at MarvyLogic has the potential to contribute towards personal growth and the enjoyment of a more fulfilling life. In this role based in Bengaluru/Bangalore, the ideal candidate must possess the fol...
Posted 2 months ago
3.0 - 7.0 years
0 Lacs
karnataka
On-site
You will be responsible for design verification at chip level to ensure that the design meets architectural and system requirements. This includes developing test environment, test bench, bus protocol checking, transaction level checking, and performance modeling. Experience in advanced verification languages such as VERA, Specman, and System C is desirable. You should have 3-5 years of solid design verification experience. A minimum educational requirement is a BS in EE, while an MS in EE is preferred. If you are interested in this position, please email your resume to careers@perfectus.com with Job Code VE in the subject line.,
Posted 2 months ago
4.0 - 8.0 years
2 - 9 Lacs
Noida, Uttar Pradesh, India
On-site
e are seeking a skilled Verification Engineer to join our team. The successful candidate will be responsible for the verification of internally developed VTLs (Veloce-friendly standard protocols such as AMBA, PCIe, SAS, Ethernet, MIPI, etc.) using various standard verification methodologies, including UVM, and ensuring signoff based on coverage matrix. Responsibilities Develop verification environments using the standard verification methodologies for protocols like PCIe, SAS, SATA, etc. Implement IP-level verification to ensure 100% functional and code coverage. Suggest and prototype various verification flows using Veloce. Integrate and qualify various VTLs with Questa-based Verification I...
Posted 3 months ago
6.0 - 11.0 years
35 - 65 Lacs
Hyderabad, Ahmedabad, Bengaluru
Work from Office
Mirafra is Hiring! OnsiteOpportunity #JoinUs Location: Any European Location (Germany, Romania Preferred) Notice Period: Immediate to 45 Days Visa : Sponsorship Available (Open to candidates from India) Exp: 7+ yrs We're looking for talented professionals with hands-on experience in Specman and NVM Digital Verification to join our global team. Key Skills: Verification planning and testbench creation Datapath, ECC, FSMs, FPGA models, and full-custom assertions Strong documentation and review presentation abilities Looking for a chance to work abroad and take your career to the next level? This is it! Apply now share your resume at: swarnamanjari@mirafra.com
Posted 5 months ago
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