DIGITAL DESIGN VERIFICATION (PHY) Marvylogic

8.0 - 15.0 years

0 Lacs

karnataka

On-site

The culture at the organization is defined by its people. There is an emphasis on fostering a culture where individuals are passionate about technology solutions that have a meaningful impact on businesses. It is also ensured that employees are encouraged to pursue their personal passions. Being a part of the team provides you with a deep insight into a variety of industries and cutting-edge technologies, enabling the creation of futuristic and impactful solutions. Moreover, the experience gained at MarvyLogic has the potential to contribute towards personal growth and the enjoyment of a more fulfilling life. In this role based in Bengaluru/Bangalore, the ideal candidate must possess the following qualifications and skills: - Proficiency in Verilog/SystemVerilog languages. - Strong expertise in UVM (mandatory) and familiarity with Specman (preferred). - Experience in formal verification is advantageous. - Knowledge of C++ is a plus. - Familiarity with Automotive, MIPI PHY standards. - Experience with PCIe and/or networking protocols (Ethernet/PCS). - Proficiency in gate-level simulation and debugging. - Proficiency in scripting languages such as Perl and Python. - Experience in SoC verification. - Strong interpersonal and communication skills. - Experience in assertion methodology and familiarity with emulation/hardware acceleration platforms is beneficial. Key Responsibilities: - Possessing 8 to 15 years of Digital Verification (DV) experience in developing and architecting verification environments, preferably from the ground up for multiple projects. - Demonstrating the ability to write test plans, enhance verification environments, and confidently code various components of a test bench (models, checkers, scoreboards, coverage monitors, etc.). - Having expertise in developing constraint random DV environments for large ASIC blocks. If you meet the qualifications and are looking for a challenging opportunity to contribute to cutting-edge technology solutions while being a part of a culture that values personal growth and fulfillment, we welcome you to apply for this position.,

Posted 2 weeks ago

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ASIC Design Verification Perfectus Technology

3.0 - 7.0 years

0 Lacs

karnataka

On-site

You will be responsible for design verification at chip level to ensure that the design meets architectural and system requirements. This includes developing test environment, test bench, bus protocol checking, transaction level checking, and performance modeling. Experience in advanced verification languages such as VERA, Specman, and System C is desirable. You should have 3-5 years of solid design verification experience. A minimum educational requirement is a BS in EE, while an MS in EE is preferred. If you are interested in this position, please email your resume to careers@perfectus.com with Job Code VE in the subject line.,

Posted 1 month ago

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VTL Design & Verification Engineer Siemens

4.0 - 8.0 years

2 - 9 Lacs

Noida, Uttar Pradesh, India

On-site

e are seeking a skilled Verification Engineer to join our team. The successful candidate will be responsible for the verification of internally developed VTLs (Veloce-friendly standard protocols such as AMBA, PCIe, SAS, Ethernet, MIPI, etc.) using various standard verification methodologies, including UVM, and ensuring signoff based on coverage matrix. Responsibilities Develop verification environments using the standard verification methodologies for protocols like PCIe, SAS, SATA, etc. Implement IP-level verification to ensure 100% functional and code coverage. Suggest and prototype various verification flows using Veloce. Integrate and qualify various VTLs with Questa-based Verification IPs. Apply customer use models within internal test suites, which may require interfacing with customers and occasional travel to customer sites. Automate and enhance methodology suites to improve verification efficiency and productivity. . Qualifications: We seek a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/VLSI from top reputed Engineering colleges with 4-8 years of significant experience in software development. Experience in EDA will be a phenomenal plus! We value you practical experience with any of the following protocols: AMBA, PCI/PCIe, SAS, Ethernet, MIPI. Experience in IP and SOC level verification. Proficiency of verification methodologies such as Specman, SV, UVM, OVM, TLM, Assertion, Coverage, co-simulation, and co-verification. FPGA/Emulation experience is helpful. Strong scripting and automation knowledge is a significant plus! Good interpersonal skills for working with external interfaces. Good problem solving and analytical skills. The person should be self-motivated and can work independently.

Posted 2 months ago

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Onsite Europe - NVM Design Verification Engineer Specman Mirafra

6.0 - 11.0 years

35 - 65 Lacs

Hyderabad, Ahmedabad, Bengaluru

Work from Office

Mirafra is Hiring! OnsiteOpportunity #JoinUs Location: Any European Location (Germany, Romania Preferred) Notice Period: Immediate to 45 Days Visa : Sponsorship Available (Open to candidates from India) Exp: 7+ yrs We're looking for talented professionals with hands-on experience in Specman and NVM Digital Verification to join our global team. Key Skills: Verification planning and testbench creation Datapath, ECC, FSMs, FPGA models, and full-custom assertions Strong documentation and review presentation abilities Looking for a chance to work abroad and take your career to the next level? This is it! Apply now share your resume at: swarnamanjari@mirafra.com

Posted 3 months ago

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