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Formal Verification Engineer

Formal Verification Engineer

Accenture

2 - 5 years

5 - 9 Lacs

bengaluru

Posted:2 hours ago| Platform:

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Skills Required

formal verification engineer python c noc soc design verification ovm uvm verilog scripting formal verification python scripting model checking ddr dram regression computer architecture design debugging programming architecture

Work Mode

Work from Office

Job Type

Full Time

Job Description

About The Role

Project Role :Formal Verification Engineer

Project Role Description :Ensure design correctness using mathematical methods like model checking and equivalence checking, without relying on simulation. Detect corner-case bugs early in the design cycle to improve quality and reduce verification time.
Must have skills :SoC Verification

Good to have skills :NA
Minimum 5 year(s) of experience is required

Educational Qualification :15 years full time education
SummaryWe are seeking experienced Design Verification (DV) Engineers to join our team for a 10-month project. This is an individual contributor role requiring deep expertise in CPU/CPU-based SoC verification, with a focus on domains such as CPU/Cache Coherency, PCIe, SoC DV, NoC/NIC (Interconnects), and DDR/HBM. The ideal candidate will be highly skilled in System Verilog, UVM, and possess strong debugging and test planning abilities. You will collaborate with architects, logic designers, and other team members to deliver high-quality, robust verification solutions.Roles & Responsibilities

Act as an individual contributor, performing assigned DV tasks independently.

Collaborate effectively with other team members to execute DV activities.

Understand architecture and micro-architecture specifications.

Work closely with Architects and Logic Designers to align on verification goals.

Develop unit-level and/or subsystem-level test plans, coverage plans, and checker plans aimed at achieving zero-defect quality post-silicon.

Design and implement scalable test benches in System Verilog and UVM.

Develop tests, functional coverage models, and System Verilog assertions.

Root cause regression failures by debugging tests/sequences, RTL, and C++ models.

Maintain high regression efficiency through test/coverage grading, compute farm, and disk utilization optimization.

Drive code and functional coverage closure.

Support debugging of unit RTL/checkers at higher integration levels, such as subsystem or top-level.Professional & Technical Skills

Solid understanding of computer architecture, SoC architecture, micro-architecture, logic design, and finite state machines (FSMs).

Strong functional verification experience, including test planning, test bench architecture, and development of test/coverage models and assertions.

Expertise in one or more of the following domains:

ARM v8/v9, RISC-V, x86 architectures

Memory architecture (DRAM, Cache, MMU), GIC, SoC debug architecture

Cache coherent architectures

PCIe OSCI layer and its functionality

PCIe PHY, bring-up, and training

SoC DV, bus interconnectsProficient in System Verilog, UVM/OVM, object-oriented programming/C++, and Python scripting.Strong debugging skills, with the ability to identify and resolve issues efficiently.Previous scripting experience is desirable.
Additional Information

Experience Required:7-10 years in design verification or related domains.

Number of Positions:3

Tentative Duration:10 months

Location:Flexible/Remote options may be available depending on project requirements.

This is an individual contributor role; candidates must demonstrate the ability to work independently and collaboratively.
Qualification 15 years full time education

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Formal Verification Engineer