Role Description This is a full-time on-site role for DFT Engineer at Incise Infotech Pvt. Ltd. DFT Engineer will be responsible for developing, implementing, and verifying the Design for testability (DFT) on complex system on chips (SOCs). The role also involves working with the physical design team to ensure the DFT requirements are met and with the verification team to ensure the DFT design is meeting the test coverage metrics. The ideal candidate will have experience in SOC level DFT techniques, ATPG, MBIST, JTAG, and boundary scan. Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering or equivalent 3+ years of experience in DFT domain Expertise in DFT methodologies - scan insertion, scan compression, boundary scan, and memory BIST Experience in DFT tools like Tessent, ATPG, MBIST, and JTAG Experience in the complete scan chain flow (ATPG, simulation, and test pattern generation) on complex SOCs Knowledge of STA, LEC, and physical design aspects related to DFT Experience in Shell/Perl/Tcl and other scripting languages Good communication skills and the ability to work well in a team environment Interested can share resume on Shubhanshi@incise.in

Layout concepts: Good knowledge in layout matching techniques and it usage Able to do floorplan, placement , routing and lvs-drc clean at block level Hands on experience in OPAMP , LDO, BGA and reference generate blocks Handle the block independently and able to communicate with design team Expertise in EM and IR fixes Good knowledge in floor planning of IPs like RX, TX and Synth IPs Understanding of DRC errors and fixing it including density errors . Good knowledge in Tsmc 6nm technology node Interested candidates can share their resumes to shubhanshi@incise.in

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Must have strong background as engineer development in electronics/ semiconductors/ software industry for 4+ Years. Knowledge of NXP product line and Automotive Market . Strong language skills (C coding). Contact at Shubhanshi@incise.in Required Candidate profile Candidate should have overall experience of Firmware development for more than 4 years. Strong background with more than one domain as firmware/ SOC/ RTOS/ Bootloader/ Security/ Automotive .

Skills : Calibre,ICC2,Perl,TCL Total vacancies : 3 Experience on EMIR analysis for multiple modes, including; static and dynamic with/without functional vectors Should have expertise in understanding and debugging EMIR issues in a block level. Power analysis for the blocks. Experience on Floor-planning, Place & route, power and clock distribution, pin placement. In-depth knowledge on industry leading tools like Redhawk, Olympus/ICC2, Primetime, and Calibre Knowledge of package modeling, package and chip level analysis is added advantage Good understanding of Physical design verification using Calibre. Knowledge of Synthesis and DFT is added advantage. Prior experience with 16nm or finer geometries is a plus. Proficient use of tcl/Perl Must have good communication skills and self-driven individual

Key Responsibilities: Develop and maintain embedded software for wireless products such as IoT devices, RF modules, BLE, Wi-Fi, LoRa, Zigbee, or LTE-based systems . Work with cross-functional teams to integrate software with custom hardware and validate end-to-end functionality. Implement and optimize protocol stacks and communication layers. Design and develop real-time embedded applications using RTOS or bare-metal environments. Interface with hardware peripherals (UART, SPI, I2C, ADC, DMA, etc.). Debug and resolve system-level issues using embedded development tools (JTAG, SWD, logic analyzers, protocol sniffers). Ensure software quality through code reviews, unit tests, and automated validation. Contribute to firmware architecture, design documents, and version control practices. Required Skills & Qualifications: Bachelors or Master’s degree in Electronics, Computer Science, Electrical Engineering, or related field. 4+ years of experience in embedded C/C++ programming . Strong understanding of wireless communication protocols such as BLE, Wi-Fi, LoRa, Zigbee, or 6LoWPAN. Proficiency with RTOS platforms (e.g., FreeRTOS, Zephyr) or bare-metal programming. Experience working with MCUs/SoCs (e.g., Nordic nRF, STM32, ESP32, TI CC series). Solid grasp of embedded system constraints (memory, power, real-time processing). Experience with version control tools like Git and development workflows.

Job Summary: We are seeking a highly skilled and experienced Senior Analog Circuit Design Engineer with 8+ years of industry experience in designing and validating precision analog circuits. The ideal candidate will have deep expertise in custom analog/mixed-signal IC design, low-noise and low-power design techniques, and strong analytical skills to drive innovation in next-generation electronic systems. Key Responsibilities: Lead the design, simulation, layout, and validation of analog and mixed-signal circuits (e.g., amplifiers, ADCs/DACs, regulators, PLLs, filters). Define architecture and specifications for analog sub-systems based on system requirements. Collaborate with layout engineers to optimize layout for performance, area, and manufacturability. Perform pre- and post-layout simulations (corner, Monte Carlo, noise, mismatch, etc.). Own and drive IP development from concept through silicon validation and production support. Conduct design reviews and provide mentorship to junior engineers. Work closely with cross-functional teams including digital design, verification, test, and packaging. Support silicon bring-up, debug, and characterization of analog blocks in the lab. Evaluate and select components for board-level analog circuitry when applicable. Qualifications: Bachelors or Master’s degree in Electrical Engineering or related field; Ph.D. preferred. 8+ years of hands-on experience in analog/mixed-signal IC design. Strong knowledge of CMOS/BiCMOS technologies. Expertise in using tools such as Cadence Virtuoso, Spectre, HSPICE, or similar EDA tools. Experience with silicon validation using lab equipment (oscilloscopes, spectrum analyzers, etc.). Proven track record of successful tape-outs and production-quality silicon. Excellent problem-solving and debugging skills. Strong communication and documentation abilities. Preferred Skills: Experience with analog front-end design for sensor interfaces or RF front ends. Familiarity with low-power design for portable/wearable devices. Understanding of layout techniques to mitigate parasitics, latch-up, and ESD. Knowledge of reliability and failure analysis (e.g., electromigration, hot-carrier effects). Experience with scripting languages (Python, Perl, TCL) for automation. Why Join Us? Be part of cutting-edge innovation in analog/mixed-signal technology. Work in a collaborative environment with industry veterans and emerging talent. Competitive compensation, performance bonuses, and comprehensive benefits. Career development opportunities and exposure to global projects. Interested candidates can share their resumes to shubhanshi@incise.in

Collaborate with the design team for the implementation of various hard IPs and the SoC top level. Lead the top-level implementation of SoC designs, including IO ring integration. Utilize Synopsys Fusion Compiler for physical and WLM synthesis. Perform timing analysis and resolve timing issues related to implementation. Conduct DFT insertion and ensure robust design for testability. Execute place and route flows using Cadence Innovus and Synopsys Fusion Compiler. Manage chip-level and block-level design implementation. Design and analyze IO rings. Implement FlipChip SoC designs, including RDL routing. Ensure timing and design signoff, including STA, LVS, and DRC. Utilize tools such as Synopsys Design Compiler, DFT Compiler, PrimeTime, Cadence Innovus, and Mentor Graphics Calibre for various implementation tasks. Interested candidates can share their resumes to shubhanshi@incise.in

About the Role: We are seeking a highly skilled and experienced Analog Layout Manager to lead our layout engineering team in the development of cutting-edge analog and mixed-signal ICs. This role requires deep technical expertise in analog layout, strong leadership capabilities, and the ability to deliver high-quality silicon in aggressive timelines. Key Responsibilities: Lead and manage a team of analog layout engineers to deliver high-quality layouts for analog and mixed-signal IPs (e.g., ADCs, DACs, PLLs, LDOs, PMICs, etc.) Own the floor planning, partitioning, and layout strategy for complex blocks and full chip integration. Collaborate closely with circuit design, verification, and physical design teams to optimize layout for performance, area, and reliability. Ensure adherence to foundry DRC/LVS/ANT/ERC/ESD guidelines and support closure of physical verification issues. Drive layout automation and CAD tool flows to improve efficiency and quality. Conduct design reviews and provide mentorship to junior layout engineers. Manage project schedules, resource planning, and risk mitigation strategies. Interface with external stakeholders including foundry, EDA vendors, and cross-functional teams. Required Qualifications: Bachelors or Masters degree in Electronics, Electrical Engineering, or related field. 8+ years of hands-on experience in analog layout and team management. Proven track record of delivering production-quality analog/mixed-signal layouts in advanced nodes (e.g., 28nm, 16nm, 7nm, or FinFET technologies). Strong knowledge of parasitic extraction, EM/IR analysis, and layout-dependent effects (LDE). Proficient in layout tools such as Cadence Virtuoso, Calibre, Assura, and Mentor Graphics. Experience in team leadership, mentoring, and performance management. Excellent communication, documentation, and project management skills. Preferred Skills: Prior experience working in a fabless semiconductor environment. Knowledge of ESD protection, latch-up rules, and analog reliability concerns. Exposure to automotive, medical, or other high-reliability standards is a plus. What We Offer: Competitive compensation and benefits. Opportunity to work on leading-edge semiconductor technology. Collaborative and inclusive work environment. Professional development and career growth. Interested candidates can share their resumes to shubhanshi@incise.in

We are seeking a highly motivated and skilled Design Verification Engineer with a strong background in UVM, SystemVerilog , and IP-level verification . The ideal candidate will be responsible for developing and executing robust testbenches, simulation, and debugging strategies to ensure first-time-right silicon. Key Responsibilities: Develop and maintain UVM-based verification environments for IP-level testbenches. Perform RTL and Gate-level simulation and debug functional issues. Define and execute comprehensive test plans to validate functional correctness. Integrate and verify AMBA bus protocols such as AHB and AXI. Develop and close assertions and functional coverage to meet verification completeness. Write reusable SystemVerilog assertions (SVA) and functional coverage models. Collaborate with design, architecture, and verification teams to debug and resolve complex issues. Utilize scripting languages ( Shell, Perl, Python ) to automate flows and enhance productivity. Participate in regular code reviews and contribute to verification process improvements. Communicate effectively across cross-functional teams and global engineering groups. Required Skills & Experience: Strong expertise in UVM and SystemVerilog for testbench development. Solid experience in RTL and gate-level simulation and debug . Hands-on experience in test planning, writing, and executing test cases . Good working knowledge of AHB/AXI bus protocols . Proficient in assertion-based verification and coverage development/closure . Working knowledge of C programming and scripting using Shell, Perl, or Python . Excellent communication, problem-solving, and team collaboration skills. Prior experience with IP-level DV and delivery is a must. Interested can share resume on Shubhanshi@incise.in

Key Responsibilities: Translate design specifications into comprehensive power specifications and architect UPF files accordingly. Build and refine power intent using Unified Power Format (UPF) at RTL and gate-level, ensuring consistency across synthesis and physical design flows. Perform power-aware checks using CLP and debug issues arising during MV cell insertion such as isolation, retention, and level shifters. Collaborate with Power Aware DV teams to address feedback and enhance the robustness of power intent. Estimate dynamic and leakage power early in the design cycle and generate power reports using tools like PTPX . Monitor and analyze power trends through implementation milestones; highlight mismatches and coordinate resolution with synthesis/PD teams. Partner with SoC, subsystem, and verification teams for accurate delivery of power intent and power estimates across project phases. Drive automation and improve analysis workflows via scripting using TCL, Perl, or Makefiles . Technical Skills: Expertise in creating and validating UPF-based power intent for SoCs with complex power domains In-depth experience in CLP-based RTL/Gate-level validation Strong command of power estimation using PrimeTime PX (PTPX) Solid knowledge of MV logic components and their insertion behavior during synthesis Clear understanding of power optimization techniques for both dynamic and leakage at various design stages Familiarity with Pre-Si/Post-Si power correlation strategies Strong scripting capabilities in TCL/Perl , with experience in managing flows through Makefiles Interested share resume or references to Shubhanshi@incise.in

Key Responsibilities: Lead end-to-end physical design flow for complex blocks or full-chip designs. Drive floorplanning, power planning, placement, CTS, routing, and physical verification (DRC, LVS). Optimize timing, power, and area to meet design specifications. Perform hierarchical/flat implementation based on project needs. Work closely with RTL, DFT, STA, and packaging teams. Manage and mentor a team of physical design engineers. Interact with EDA vendors to improve tool flows and resolve tool-related issues. Contribute to methodology improvements and script automation for design efficiency. Required Skills and Qualifications: B.Tech/M.Tech in Electronics/Electrical Engineering or related field. 8+ years of hands-on experience in physical design with deep expertise in block and full-chip implementation. Strong knowledge of EDA tools: Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, RedHawk/Totem, etc. Solid understanding of STA, IR/EM analysis, congestion analysis, and ECO implementation. Experience on advanced nodes (7nm/5nm/3nm) is highly desirable. Prior leadership or team management experience. Strong debugging, scripting (Tcl, Perl, Python), and communication skills.

What Youll Work On: Develop and execute UVM-based testbenches for IP/SoC verification Write test plans, assertions, and coverage to ensure design quality Debug issues in simulation and collaborate with design & DFT teams Work on block-level and system-level verification Use tools like VCS, Questa, Verdi, Jasper , etc. What We’re Looking For: 3+ years of hands-on experience in UVM/RTL verification Strong understanding of verification methodology, SystemVerilog, SVA Experience with debugging tools and coverage analysis Solid scripting skills (Python/TCL/Perl) a big plus Exposure to complex SoCs or multi-clock domain verification is a bonus

• 3+ years of solid experience in IP/SoC design • Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts • Good knowledge of Digital Design and RTL development • Hands-on experience with SoC Design, Verilog RTL coding • Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug • Working knowledge of Lint, CDC, PLDRC, CLP etc • Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification • Manage SoC dependencies, planning and tracking of all front-end design related tasks • Working for successful design delivery for the project milestones across the design, verification and physical implementations • Should possess effective communication skills Interested candidates can share their resumes to shubhanshi@incise.in

Strong Debug, UVM, System Verilog Understanding Specs and Standards and developing relevant test plans Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Preferred Qualifications 5+ Year of industry experiences in the following areas: - Thorough understanding of Digital design concepts Thorough understanding dv methodologies and tools Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5) Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Interested can share resume on Shubhanshi@incise.in

Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in PnR tools like ICC/Innovus with regards to physical convergence must. Good understanding of PD flows and overall backend tool flow would be beneficial. Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and DRV. TCL/PERL Scripting is plus. Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable. Interested candidates can share their resumes to shubhanshi@incise.in

Should be skilled in INNOVUS,Fusion compiler and Calibre must have worked on latest Tech nodes , with very good hand on experience with PV flows like DRC.ERC,Perc,antenna ,ESD checks , should have atleast basic knowledge on handling tcl scripting

Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 3+ years of relevant experience.Strong in UVM/System Verilog/C/C++/scripting, Simulation, Formal verification. Good understanding of SoC architectures Required Candidate profile GLS verification experience at Core level. SV - UVM understanding. Scripting in perl, python. Debug of complicated designs using Verdi. Power aware verification, SDF / timing simulation.

Roles and Responsibilities Good experience in PD execution of multiple medium to High critical blocks/HMs from Netlist to GDSII Develop and qualify the methodology and implementation flow in advanced technologies like 14nm and below. Well versed with FC/Innovus tools and good understanding of place/cts/Route critical settings Develop expertise in ASIC Synthesis, Floor Planning, STA (Static Timing Analysis), and other relevant technologies. Good experience in Low power designs Conduct thorough analysis of designs to identify potential issues and implement solutions. Perform physical design activities including floor planning, PNR (Physical Netlist) creation, and timing closure using Innovus tools. Interested candidates can contact me at shubhanshi@incise.in

Key Responsibilities: Develop and execute Plans of Record including schedules, budgets, resources, and risk management. Lead program tracking , stakeholder communication, and milestone achievement. Drive dashboard planning and implementation to support program visibility and decision-making. Collaborate with internal and external stakeholders on technical and operational matters. Identify and mitigate risks, manage program metrics, and ensure alignment with strategic goals MUST Require Skills & Competencies: Strong understanding of VLSI design flows (front-end and back-end). (6-10) years of experience into PM in VLSI Proficiency in program management tools (dashboards, Gantt charts, etc.). Excellent analytical , communication , and decision-making skills. Ability to work independently and influence cross-functional teams. Experience in data interpretation , risk management , and process improvement . The ideal candidate will be proficient in different dashboard requirements planning and implementation tracking, with background of VLSI front-end and back-end. VLSI front-end include RTL design, verification (block level, top level), synthesis, formal, DFT, low power, emulation prototyping and VLSI back-end includes physical design areas including placement, routing, STA, PV, PDN signoff activities. The candidate should drive high-performance execution in a dynamic environment. General Summary Develops, defines, and executes plans of record, including: schedules, budgets, resources, deliverables, and risks