Posted:2 weeks ago|
Platform:
Work from Office
Full Time
Key Responsibilities: Lead end-to-end physical design flow for complex blocks or full-chip designs. Drive floorplanning, power planning, placement, CTS, routing, and physical verification (DRC, LVS). Optimize timing, power, and area to meet design specifications. Perform hierarchical/flat implementation based on project needs. Work closely with RTL, DFT, STA, and packaging teams. Manage and mentor a team of physical design engineers. Interact with EDA vendors to improve tool flows and resolve tool-related issues. Contribute to methodology improvements and script automation for design efficiency. Required Skills and Qualifications: B.Tech/M.Tech in Electronics/Electrical Engineering or related field. 8+ years of hands-on experience in physical design with deep expertise in block and full-chip implementation. Strong knowledge of EDA tools: Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, RedHawk/Totem, etc. Solid understanding of STA, IR/EM analysis, congestion analysis, and ECO implementation. Experience on advanced nodes (7nm/5nm/3nm) is highly desirable. Prior leadership or team management experience. Strong debugging, scripting (Tcl, Perl, Python), and communication skills.
Incise Infotech
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