234 Formal Verification Jobs - Page 5

Role Responsibilities: Verify complex digital design blocks (e.g., GPU, CPU, Image processors) by analyzing design specifications and working with design engineers. Create and enhance constrained-random verification environments using SystemVerilog, UVM, or formal verification techniques with SystemVerilog Assertions (SVA). Write coverage measures for stimulus and corner cases, ensuring thorough testing of the design. Debug tests in collaboration with design engineers to ensure functional correctness and close coverage gaps before tape-out. Job Requirements: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering, or equivalent practical experience. 3 years of experience with standard GPU workloads like Manhattan/3DMark and knowledge of GPU architecture. Experience with AMBA Bus protocols like AHB/AXI/ACE. Experience in creating verification environments and debugging designs.

As a Senior Formal Verification Engineer specializing in CPUs, you will be responsible for the property-based formal verification of the CPU core, pipeline stages, and subcomponents with exhaustive proof goals. Your role will involve leading formal planning and methodology for control logic, pipelines, and memory subsystems. You will define safety and liveness properties, model check for corner case behavior, and guide designers in writing formal-friendly RTL and assertions. Additionally, you will analyze convergence issues, coverage gaps, and create abstraction models, while integrating formal sign-off into project milestones. To excel in this role, you should have a minimum of 8 years of formal verification experience with CPUs or processors. Proficiency in tools such as JasperGold, VC Formal, OneSpin, or equivalent is required. Expertise in SVA/PSL, abstraction modeling, and formal coverage closure is essential. A strong background in computer architecture, particularly in pipeline, MMU, and interrupt logic, will be beneficial. You should possess excellent problem-solving skills, convergence debugging abilities, and strong documentation skills. If you meet these requirements and are interested in this opportunity, please submit your updated CV to janagaradha.n@acldigital.com.,

SE NIOR SILICON DESIGN ENGINEER 1. Must have SoC implementation knowledge with deep level expertise in at least one domain. Have responsibility for processes of significant technical importance and for results in SoC implementation and/OR related areas. Solve complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation. Influences technical decisions that have a significant impact on final product. Requires limited supervision and is evaluated according to project performance. Coaches and mentors less experienced staff; influences others as a technical leader. very good communication and presentation skills Proficiency in scripting Required Skills: SoC implementation expertise. Multi million gates integration. Low power implementation, Constraints validation, Formal verification Floorplanning, Power planning. Clock Tree Synthesis (CTS). Awareness of Synthesis, SCAN and DFT implementation Static Timing analysis (STA). Analysis: IR, EM, Noise. Physical Verification #LI-PK2

As a highly experienced Verification Engineer at our dynamic team, you will drive innovation in advanced verification methodologies for complex semiconductor designs. Your key responsibilities will include leading the deployment of verification tools, platforms, and strategies for complex IPs, driving simulation-based and hardware-assisted verification efforts, applying expertise in various verification technologies, developing and enhancing verification methodologies, collaborating cross-functionally with IP design and DV teams, and mentoring junior engineers to foster a culture of technical excellence. You should have 10+ years of experience in verification engineering for complex hardware systems, deep expertise in simulation and debug, hands-on experience with Static/Formal verification tools and methodologies, exposure to hardware-assisted verification environments, strong analytical and problem-solving skills, a degree in Electrical Engineering, Computer Engineering, or related field, familiarity with industry-standard verification languages, experience with scripting and automation, and a track record of technical leadership and cross-functional collaboration. Join our team at Synopsys and be part of an environment that values agility, courage, excellence, and trust. You will have the opportunity to work on cutting-edge technology and make a real impact.,

Job Description In your new role you will: Create and define verification plans for SOC integration verification; Develop verification environments for our ICs using UniversalVerification Methodology (UVM ). Develop test scenarios using SystemVerilog and SW based C/CPP tests . Utilise Perspec/PSS portable stimulus tooling to enable randomised SW based tests. Develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies; Work closely with IP verification teams to align work split and information sharing. Your Profile You are best equipped for this task if you have: You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least two years of experience in Constrained-Random Metric-Driven Verification or SOC integration verification. You have capabilities and experience in working with microcontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog. You have some knowledge of SW-based testing (writing/executing SW on embedded CPUs) Have knowledge of RTL design (System Verilog); Ideally have knowledge of working with Verification IPs (VIPs) Contact: Gowri Shenoy, LinkedIn We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Are you interested in working with a world-class CPU design teamAre you interested in the application of formal methods to the verification of application processorsIn contributing to the development of the next generation of formal methodologies in this space Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalization of the refinement from architecture to micro-architecture Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components Engage in full-spectrum deployment of model-checking technology to hardware designs including property verification, math proofs, architectural modeling and validation amongst other cutting-edge application areas To be successful in this position you will need BA/BS degree in CS/EE with 8+ years of practical experience in application of formal methods in hardware or software Strong model checking or theorem proving background/experience in verification of complex systems Experience in writing assertions and associated modeling code in Hardware Description Languages or in proving correctness of architectural specifications using formal methods Working familiarity with model checkers like Jaspergold and VC-Formal or theorem-proving tools such as ACL2 and HOL The ideal candidate will have the following experience MS/PhD degree in CS/EE; 4+ years of practical experience Strong foundation in formal methods and in their application to hardware specifications and/or implementations Domain knowledge in one or more of these areasMicroprocessor architecture and micro-architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, security architectures Strong software engineering skills with proven ability in automation and proficiency in at least one programming language (C++, Python, TCL etc.) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. * Hands on PD execution at block/SoC level along with PPA improvements * Strong understanding of the technology and PD Flow Methodology enablement. * Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area/power/performance/convergence), develop plans and deploy/support them * Provide tool support and issue debugging services to physical design team engineers across various sites * Develop and maintain 3rd party tool integration and productivity enhancement routines * Understand advance tech PNR and STA concepts and methodologies and work closely with EDA vendors to deploy solutions. Skill Set * Strong programming experience & Proficiency in Python/Tcl/C++ * Understand physical design flows using Innovus/fc/icc2 tools * Knowledge of one of Encounter/Innovus or FC (or other equivalent PNR tool) is mandatory * Basic understanding of Timing/Formal verification/Physical verification/extraction are desired * Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 3-5 years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory* Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications: 6 -15 years of High Performance core Place & Route and ASIC design Implementation work experience (A Must) Preferred Qualifications Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Good knowledge of Tcl/Perl Scripting Strong problem-solving skills and good communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3- 6yrs years of experience in Physical Design/Implementation Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: : We are seeking a highly skilled and experienced Senior Formal Verification Engineer to join our dynamic team. The ideal candidate will have a strong background in formal verification methodologies and tools, with a proven track record of verifying complex IPs. You will play a critical role in ensuring the quality and reliability of our cutting-edge IPs. Key Responsibilities: Develop and execute formal verification plans for complex IPs. Collaborate with design and verification teams to define verification strategies and methodologies. Create and maintain formal verification environments using industry-standard tools. Identify and debug issues in the design using formal verification techniques. Provide technical guidance and mentorship to junior team members. Work closely with cross-functional teams to ensure seamless integration of IPs. Continuously improve verification processes and methodologies. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 8-12 years of experience in formal verification. Proficiency in formal verification tools such as JasperGold, Cadence IFV, or similar. Strong understanding of digital design and verification methodologies. Experience with SystemVerilog, UVM, and other verification languages. Excellent problem-solving and debugging skills. Strong communication and teamwork skills. Ability to work independently and manage multiple tasks effectively. Preferred Qualifications: Experience with verification of high-performance IPs. Knowledge of scripting languages such as Python or Perl. Familiarity with version control systems like Git. Why Join Us: Opportunity to work on cutting-edge technology and innovative projects. Collaborative and inclusive work environment. Competitive salary and benefits package. Professional growth and development opportunities. If you are passionate about formal verification and want to be part of a team that is pushing the boundaries of technology, we would love to hear from you! Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Masters degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Requirements Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Develop and improve existing flow for logical equivalent check Experience with ABORT/NEQ debugging process Hands- on in logical equivalence tools such as Conformal LEC and/or Formality Understanding cross-functional RTL/PD/DFT teams Perl, Python, TCL

At Cadence, we are looking for individuals who are passionate about technology and aspire to lead and innovate in the industry. Your responsibilities will include understanding and reviewing design specifications, developing verification strategies, test plans, and coverage plans. Additionally, you will be tasked with creating constrained random verification environments, verification components, writing tests, sequences, functional coverage, and assertions to achieve verification goals. Furthermore, you will be developing C-based test cases for SOC verification. To excel in this role, you should have a strong background in functional verification fundamentals, environment planning, test plan generation, and environment development. Proficiency in System Verilog and experience with UVM based functional verification environment development are required. Knowledge of verilog, vhdl, C, C++, Perl, and Python is essential. Expertise in AMBA protocols such as AXI, AHB, and APB is a must, along with familiarity with USB, PCIE, Ethernet, DDR, LPDDR, or similar protocols. Proficiency in version control and load sharing software is also necessary. Desirable skills and experience include prior experience with Cadence tools and flows, familiarity with ARM/CPU architectures, experience in developing C-based test cases for SOC verification, some exposure to assembly language programming, and knowledge of protocols like UART, I2C, SPI, and JTAG. Embedded C code development and debug, as well as formal verification experience, would be advantageous. Strong communication, organizational, planning, and presentation skills are crucial for success in this role. You should be able to work independently, deliver high-quality results in a fast-paced environment, and be open to learning new methodologies, languages, and protocols. Personal development and growth are essential to meet the evolving demands of the semiconductor industry. A self-motivated mindset and willingness to take on additional responsibilities to contribute to the team's success are highly valued. Join us at Cadence, where we tackle challenges that others cannot. Let's make a difference together.,

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

Qualcomm India Private Limited is a company of inventors at the forefront of 5G technology, unlocking new possibilities that will revolutionize industries, create job opportunities, and enhance lives. As part of the Engineering Group in the Hardware Engineering division, you will be joining a dynamic team responsible for designing Low Power controller IP cores and subsystem digital design for cutting-edge Snapdragon SoCs used in mobile, compute, IoT, and Automotive markets globally. In this role based at Qualcomm's Bangalore office, your key responsibilities will include micro-architecture and RTL design for Cores/subsystems, collaborating closely with Systems, Verification, SoC, SW, PD & DFT teams, enabling software teams to utilize hardware blocks, qualifying designs through static tool checks, and reporting progress status against expectations. Preferred qualifications for this position include 5 to 10 years of experience in digital front-end design (RTL design) for ASICs, expertise in RTL coding in Verilog/SV/VHDL, familiarity with UPF and power domain crossing, experience in synthesis, logical equivalence checks, RTL and netlist CLP, proficiency in various bus protocols, low power design methodology, clock domain crossing designs, formal verification, and database management flows. Additionally, expertise in Perl/TCL/Python language, post-Si debug, and strong communication skills are valued qualities for this role. To be considered for this opportunity, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of relevant work experience, or a PhD with 2+ years of related work experience. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. Please reach out to disability-accommodations@qualcomm.com for support. The company expects its employees to comply with all applicable policies and procedures, including confidentiality requirements. If you are a staffing or recruiting agency, please note that Qualcomm's Careers Site is exclusively for individual job seekers, and submissions from agencies will be considered unsolicited. For more information about this role, please contact Qualcomm Careers directly.,

Roles and Responsibility Senior IO-MMU Verification Engineer Role Overview: Responsible for functional verification of IO-MMU units, focusing on translation, protection, and system interaction with DMA/IP blocks. Key Responsibilities: Develop UVM-based environments for IO-MMU verification Create tests for virtual address translation, permissions, and fault injection Verify compliance with protocols like PCIe ATS, PRI, and ARM SMMU Collaborate with SoC-level teams for system integration and validation Drive functional and code coverage closure Required Skills: 8+ years in verification of memory or IO subsystems Expertise in UVM, SystemVerilog, SVA Strong debugging and protocol knowledge (AXI, PCIe, SMMU) Experience with constrained-random and assertion-based verification Familiar with trace analysis and formal verification integration

Qualification Check is a global leader in education, offering services in 195 countries and 50,000 institutions. Our secure managed service conducts verification at the source with a detailed audit trail to uphold transaction integrity. With the support of a multi-lingual team proficient in languages like English, Arabic, Hindi, Spanish, Italian, Russian, and Portuguese, we authenticate candidates" academic and professional credentials. Based in the UK, we provide global coverage and expertise to our clientele. This full-time, on-site position in Gurugram is for a Senior Verification Specialist in Education. The Senior Verification Specialist will be responsible for overseeing verification processes, which include insurance and formal validation of educational and professional qualifications. Daily responsibilities involve analyzing verification data, liaising with institutions and clients, and delivering exceptional customer service to ensure precise and efficient verifications. The ideal candidate for this role should possess strong analytical skills for data analysis and verification procedures. Prior experience in Education Verification and Formal Verification techniques is preferred. Excellent communication skills are essential, along with the ability to manage multiple tasks efficiently and collaborate effectively within a team. Previous exposure to the education or verification industry would be advantageous. A Bachelor's degree in a relevant field or equivalent professional experience is required.,

MTS SILICON DESIGN ENGINEER THE ROLE: Execute formal verification for complex blocks for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: Good knowledge of formal verification along with understanding of complex designs. KEY RESPONSIBILITIES: Understand the design to be verified Plan and execute formal verification. Formal test plan documentation. Estimate the time required for formal verification, coverage and clock gating checks. Build the formal property verification/datapath verification environments. PREFERRED EXPERIENCE: 7+ years of formal verification experience . Familiarity with CPUs/GPUs/Cache is desirable. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1

Job Requirements Develop and execute verification plans for SoC-level designs. Build UVM/SystemVerilog-based testbenches integrating multiple IPs. Write and maintain testcases, sequences, assertions, and coverage models. Perform functional, system, and performance verification. Debug simulation failures and collaborate closely with designers and architects. Drive coverage closure and track verification metrics. Support emulation and FPGA prototyping environments as needed. Mentor junior engineers and contribute to process improvements. Required Skills Strong experience in SystemVerilog and UVM methodology. Good understanding of SoC architectures, interconnects (AXI, AHB), and protocols. Hands-on expertise in random constrained stimulus generation and functional coverage. Proficiency in debug tools (SimVision, Verdi, DVE). Experience with simulation tools (VCS, Questa, Incisive). Exposure to gate-level simulations, power-aware verification, and low-power design concepts. Knowledge of scripting (Perl, Python, Tcl). Good to Have Experience in emulation platforms (Palladium, Veloce). Familiarity with formal verification techniques. Knowledge of cache coherency protocols and memory subsystems Education B. E/B. Tech or M. E/M. Tech in Electronics, related field. Work Experience Required Skills Strong experience in SystemVerilog and UVM methodology. Good understanding of SoC architectures, interconnects (AXI, AHB), and protocols. Hands-on expertise in random constrained stimulus generation and functional coverage. Proficiency in debug tools (SimVision, Verdi, DVE). Experience with simulation tools (VCS, Questa, Incisive). Exposure to gate-level simulations, power-aware verification, and low-power design concepts. Knowledge of scripting (Perl, Python, Tcl).

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors. Siemens EDA is a global technology leader in Electronic Design Automation software. Their software tools empower companies worldwide to develop innovative electronic products efficiently. By using these tools, customers are able to advance technology and physics boundaries to deliver superior products in the complex realm of chip, board, and system design. This is your role. Aprisa provides comprehensive functionality for top-level hierarchical design and block-level implementation for intricate digital IC designs. The detail-route-centric architecture and hierarchical database at Aprisa facilitate the acceleration of design closure and attainment of optimal quality results within a driven runtime. Aprisa is currently engaged in developing the next-generation RTL-to-GDSII solution and is seeking individuals to join this pioneering journey. **Role:** - Drive and oversee the design and development of various aspects of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Guide and lead team members towards successful project completion by introducing innovative and effective solutions. - Collaborate with a dedicated team of experts. **Must-Have Requirements:** - Bachelor's or Master's degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Proficient in C/C++, algorithms, and data structures. - Strong problem-solving and analytical skills. - Leadership abilities to inspire and support the team with your expertise. **Great to Have Experience in:** In this role, you will have the opportunity to work with RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Furthermore, you will be involved in designing C or RTL IPs, optimizing RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly appreciated, along with your proficiency in scripting languages like Python and TCL. Join Siemens, a diverse collective of over 377,000 individuals shaping the future in more than 200 countries. Siemens is committed to equality and encourages applications that reflect the diversity of the communities where they operate. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help shape tomorrow!,

Join Our Aprisa Team! Aprisa is looking for Siemens EDA ambassadors who are passionate about electronic design automation software. As a global technology leader, Siemens EDA provides innovative tools that empower companies worldwide to develop cutting-edge electronic products efficiently. By utilizing our software solutions, our customers can navigate the complexities of chip, board, and system design while pushing the boundaries of technology and physics to deliver superior products. Your Role: As part of the Aprisa team, you will play a crucial role in the development of top-level hierarchical design and block-level implementation for complex digital IC designs. Leveraging our detail-route-centric architecture and hierarchical database, you will expedite design closure and achieve optimal quality results within a driven runtime. Join us in shaping the next-generation RTL-to-GDSII solution and become an integral part of this innovative journey! Key Responsibilities: - Drive and oversee the design and development of various components of RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. - Provide guidance and leadership to ensure successful project completion through innovative and effective solutions. - Collaborate with a dedicated team of experts to achieve common goals. Requirements: - Hold a B.Tech or M.Tech degree in CSE/EE/ECE from a reputable engineering college with 8-12 years of experience in software development. - Possess a strong grasp of C/C++, algorithms, and data structures. - Demonstrate exceptional problem-solving and analytical skills. - Lead and motivate the team with your expertise. Desirable Experience: You will have the opportunity to: - Develop RTL synthesis tools and engage with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. - Design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. - Utilize parallel algorithms and job distribution strategies, along with proficiency in scripting languages like Python and TCL. Join Siemens: Siemens is a global community of over 377,000 individuals working together to shape the future across 200 countries. We value diversity and equality, and we welcome applications that represent the various communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business requirements. Embrace your curiosity and creativity to help us pioneer tomorrow!,

: As part of the methodology team, you will lead the development, improvement, and deployment of low power structural check methodologies across multiple SoC and IP projects. This role involves designing automated flows for UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. You will collaborate closely with design, verification, and EDA partners to ensure robust, scalable, and high-coverage power-aware design signoff strategies across technology nodes and product segments. Responsibilities: Develop and maintain low-power structural check methodologies (UPF/CPF validation, isolation, level shifters, retention, domain crossings). Build automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP. Ensure power intent consistency and early issue detection through collaboration with design and verification teams. Integrate structural checks into signoff regressions with high coverage and low false positives. Work with vendors and internal teams to enhance tools, debug issues, and improve efficiency. Drive global adoption through documentation, training, and support. Assist in audits, quality reviews, and milestone checks. Required Skills and Experience : 5+ years of Strong background in low-power structural methodologies and UPF/CPF-based flows. Deep understanding of power intent specs, domain partitioning, isolation, and retention. Hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP. Skilled in scripting (Python, Perl, TCL) for flow automation. Experience with large SoC/IP designs across advanced nodes. Confirmed ability to debug structural issues and drive closure. Strong communication and documentation skills. Nice To Have Skills and Experience : Experience with formal verification or functional simulation for power-aware designs. Knowledge of complex power analysis and correlation with structural checks. Exposure to hierarchical low-power signoff strategies in multi-voltage or multi-power domain SoCs. Familiarity with power-aware DFT, scan strategies, and low-power aware synthesis flows. Participation in industry working groups (e.g., Accellera UPF), technical conferences, or publications. Involvement in tool benchmarking, vendor collaborations, and internal tool qualification projects. In Return: We are proud to have a set of behaviors that reflects who we are and guides our decisions, defining how we work together to surpass ordinary and shape outstanding! Partner and dedication towards or customers Collaborate and communication Originality and resourcefulness Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com. To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Hybrid Working at Arm #LI-BB1 Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation