Implementation Engineer, ASIC

As an Implementation Engineer at Kinara, a Bay Area-based venture backed company, you will play a crucial role in leading and executing Synthesis and Static Timing Analysis (STA) for complex AI SoC designs with multi-mode and multi-power domain functionalities. Your responsibilities will include: - Conducting Synthesis and STA to ensure the quality and reliability of our products - Optimizing designs for low power and high performance with logically equivalent RTL - Implementing ECOs for functional and timing closure - Working with multi-clock, multi-power domain designs and multi-mode timing constraints - Inserting DFT and collaborating with different functional teams like RTL Design, DFT, and Physical Design - Demonstrating deep understanding of physical design concepts such as floor-planning, placement, congestion, and setup/hold timing closure Qualifications required for this role: - Bachelors or Masters degree in Electronics, Computer Science Engineering, or a related field - 5 to 7 years of experience in Implementation flows, Synthesis, and STA - Proficiency in Cadence, Synopsys, and Mentor tools - Experience with Verilog, VHDL, Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks - Familiarity with Formal verification, Conformal ECO, Low power synthesis, Physical Aware synthesis, and Writing Timing Constraints - Flow Automation and Scripting using TCL, Python, or Perl At Kinara, we provide an innovative environment where technology experts and passionate professionals collaborate on exciting challenges. Our team values diverse perspectives and shared responsibilities. If you are ready to make your mark in the world of edge AI, we look forward to reviewing your application. Join us at Kinara and be a part of revolutionizing what people and businesses can achieve with AI solutions.,