234 Formal Verification Jobs - Page 6

Develop Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem and SoC. Directed and Random Verification at IP, Subsystem and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals. Perform Functional and Code Coverage Analysis. Experience and Skills Required 5 to 15 years of experience in IP SoC Verification. Expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage and Functional Coverage analysis. Development of Verification IP and Testbenches. Experience with AMS simulations desired. Must have strong debug and analytical capabilities, root cause analysis. In-depth understanding of SoC Design Flow, RTL Implementation, Analog Circuit models. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Qualcomm India Private Limited is seeking a talented individual to join their Hardware Engineering team. As a part of the Engineering Group, you will be responsible for ASIC design with a focus on digital front end design. The ideal candidate should hold a PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with 3-5 years of relevant experience in ASIC design. Key responsibilities include RTL coding in Verilog/VHDL/SV for complex designs with multiple clock domains, expertise in bus protocols like AHB, AXI, and NOC designs, and experience in low power design methodology and clock domain crossing designs. Additionally, the candidate should have experience in Spyglass Lint/CDC checks, waiver creation, formal verification with Cadence LEC, and understanding of the full RTL to GDS flow to collaborate with DFT and PD teams. Desired qualifications for this role also include experience in mobile Multimedia/Camera design, DSP/ISP knowledge, working knowledge of timing closure, expertise in Perl, TCL language, post-Si debug, and good documentation skills. The ability to create a unit level test plan is essential for this position. Minimum qualifications for this role include a Bachelor's degree with 4+ years of Hardware Engineering experience, a Master's degree with 3+ years of relevant experience, or a PhD with 2+ years of related work experience. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you are looking to be a part of a dynamic team where your skills and expertise will be valued, consider applying for this exciting opportunity at Qualcomm India Private Limited. For further information about this role, please reach out to Qualcomm Careers.,

SE NIOR SILICON DESIGN ENGINEER Role: The ideal candidate is a person with extenstive experience in applying formal verification methods to complex IPs for cpu, gpu and high speed protocols. Responsibilities: Complete ownership and execution of formal verification of cache controllers, computational IPs, floating point units, etc In this role, he/she would be responsible for formal verification of GPU Design by meeting the demands of the constantly evolving project schedule. The successful candidate will be a member of the GFX team. He/she will demonstrate passion towards design, design verification, be a teammate, a problem solver with independence, creativity, and interpersonal skills. Complete ownership and execution of formal verification of cache controllers, computational IPs, floating point units, etc. PREFERRED EXPERIENCE: Vast and deep experience of formal verification methods Domain knowledge in cpu, gpu, serial protocols Must be able to do compexity reduction, bug hunting or similar methods ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-NS1

PMTS - GFX Verification Technical Lead Role: We are currently seeking a highly skilled Principal Member of technical staff (PMTS) Verification engineer for GFX top level end-to-end verification. Responsibilities: In this role, he/she would be the technical lead responsible for driving content, quality and debug throughput of top-level debugs coming from simulation, emulation, and post-silicon debugs. Working with architects and design leads and driving quality test plans Developing verification infrastructure and needed improvements Developing content strategy for quality. Driving DV closure to meet schedule with quality Working with each domain (sub-system) lead and guide them to get better quality and debug throughput. Helping management with risk assessment on features, quality, and schedules Working with sub-system DV leads to identify potential areas of formal verification Requirements: BS +14 years or MS +12 years work experience preferred. Should have end to end GFX/Compute verification experience and system knowledge. Experience with advanced verification methodologies and languages like UVM, system Verilog. Familiarity with all Design areas and tools and confirmed understanding of design/technology interactions Good understanding of memory hierarchy, caches, address translations schemes. Good understanding of general dram technologies and address translation schemes Familiarity with GFX pipeline and GPU design is plus Familiarity with Computer organization/architecture. Strong analytical/problem solving skills and pronounced attention to details. Formal property-based verification knowledge is an added plus. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE / Electrical Engineering / Computer Engineering #LI-NS1

Required Qualifications System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills. Experience 8- 10 years Preferred Qualifications From-scratch development of IP or SoC testbenches Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262) Background with power-ware (UPF) and gate-level simulations (GLS) Ownership of complete verification cycle (verification planning -> coverage closure) in a project Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs

Job Title Required Qualifications System Verilog, UVM, C Scripting languages (Python, Tcl, Perl) Understanding of bus protocols (AXI, AHB, APB, etc.) Proven written and verbal technical communication skills Ability to collaborate in a team environment Excellent analytical and problem-solving skills. Preferred Qualifications From-scratch development of IP or SoC testbenches Familiarity with RISC-V architecture, Functional Safety Standards (ISO 26262) Background with power-ware (UPF) and gate-level simulations (GLS) Ownership of complete verification cycle (verification planning -> coverage closure) in a project Use of formal verification, particularly connectivity, to confirm SoC connectivity requirements Knowledge of UVM Register Abstraction Layer (RAL) and integration of 3rd party VIPs Experience 4-5 years

You will be joining a leading training institute in the semiconductor industry that is constantly seeking dedicated individuals who are enthusiastic about achieving excellence and eager to expand their knowledge. Our work environment is dynamic, fostering innovation and creativity, and we provide avenues for personal and professional growth through training programs, mentorship, and coaching. The position available is for Synthesis/STA in either Bengaluru or Noida with a requirement of 3-12 years of experience and a BTECH/MTECH qualification. Key Responsibilities: - Demonstrated proficiency in timing concepts and the ability to independently close timing of Block/SoC. - Hands-on experience in generating constraints. - Proficiency in Logical synthesis tools such as Design compiler/ Rc compiler. - Familiarity with Formal Verification and comfortable using LEC/formality tools. - Ability to generate and implement functional Ecos. - Experience in Pre-layout and Post layout timing analysis using industry standard tools like Primetime/ETS. - Hands-on experience in crosstalk timing closure. - Understanding of Path based analysis, AOCV, DMSA is advantageous. - Knowledge of the complete physical Design flow is considered a plus. If you are a self-driven, innovative individual with a strong commitment to excellence, we encourage you to submit your resume and cover letter to our HR department. Be part of our dedicated team of professionals and contribute to the advancement of the semiconductor industry.,

As a Formal Verification Engineer at AMD, you will play a crucial role in the Advance Formal Verification team, dedicated to providing formal functional and security verification for a variety of IPs. Your expertise in IP verification, formal verification methodologies, and high-speed IO bus protocols will be instrumental in ensuring the highest level of design quality through cutting-edge formal verification technologies. Your responsibilities will include collaborating with architects and designers to understand design intents, creating and executing formal verification plans, writing and debugging properties for design verification, optimizing runtime using formal techniques, and reporting status and progress. For senior positions, you will lead and coordinate verification activities for a small team, train junior engineers, develop working procedures, flows, and infrastructure, and handle complex formal problems. The preferred experience for this role includes 12+ years of combined ASIC/FPGA design and verification experience, expertise in formal property verification, sequential equivalence checking, and academic formal methods. You should be well-versed in formal property languages, abstraction techniques, formal sign-off, and commercial formal tools, with extensive experience in verifying complex designs and high-speed protocols. Familiarity with industry-standard protocols such as PCIe, SATA, USB, and AXI, as well as hardware-firmware interaction verification, is highly desirable. To qualify for this position, you should hold a BS (or higher) degree in Electronics/Electrical or Computer Engineering. This role is based in Bangalore, India, offering an opportunity to contribute to AMD's mission of building great products that accelerate next-generation computing experiences. Join AMD's transformative journey and be part of a team that pushes the limits of innovation to solve the world's most important challenges. Together, we advance the future of technology.,

Qualcomm India Private Limited is a leading technology innovator that strives to push the boundaries of what is possible, enabling next-generation experiences and driving digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams will be essential to develop solutions and meet performance requirements. To be eligible for this position, you should have a Bachelor's/Master's/PhD degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with relevant work experience ranging from 4 to 6+ years. Join Qualcomm's design verification team and be involved in verifying high-speed mixed-signal IP designs for products targeted for 5G, AI/ML, compute, IoT, and automotive applications. Responsibilities will include defining test plans, developing testbenches using advanced verification methodologies, authoring assertions, developing test cases, and collaborating with various teams to ensure successful verification and integration. Qualified candidates should possess a Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with at least 12+ years of ASIC design verification experience. Knowledge of HVL methodologies like SystemVerilog/UVM and experience with ASIC simulation/formal tools are required. Preferred qualifications include experience with low power design verification, formal verification, gate-level simulation, knowledge of standard protocols, scripting languages like Python or Perl, and experience with mixed-signal IP design verification. Qualcomm is an equal opportunity employer that is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this role, please contact Qualcomm Careers.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, ComputerScience, a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience developing and maintaining verification testbenches, test cases,and test environments. Preferred qualifications: Master s degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience with low power, debug, Gate Level Simulation (GLS), formal verification. Experience in driving cross functional teams for quality tape-outs Experience leading design verification of IPs, successfully delivered to many SoCs. Experience in driving or owning Sub system level verification and navigating the dependencies with Stakeholders. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the verification of digital design blocks at Sub System level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SVA and industry leading formal tools. Debug tests with design engineers to deliver functionally correct design blocks. Participate with architecture, design teams, Sival and Software (SW) teams in defining the overall verification strategy of our SoCs. Be the primary point of contact for functional verification of the IP for cross-functional teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification). Experience with programming languages (e.g., Python/Perl and TCL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or a related field. Experience with regression setup and management. Experience with formal sign-offs of industry Application-specific integrated circuit (ASIC) designs. Knowledge of formal verification applications such as sequential equivalence checking, and connectivity checking and data-path verification. Knowledge of formal methodology and formal abstraction techniques. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the formal verification strategy, create the properties and constraints for digital design blocks. Use different formal verification applications to resolve multiple tests like clock-gating verification, low power, connectivity and security path verification. Utilize formal property verification tools combined with formal verification closure techniques to verify properties. Contribute improvements to methodologies and scripting to enhance formal verification results.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Basic Qualifications : Bachelor s degree in electrical engineering (EE) is required; a master s or PhD in EE is preferred. Additional background in Math or Computer Science is highly desirable. 8+ years of experience in formal verification or 7+ years of experience in traditional design verification (DV). Strong professional work ethic with the ability to manage and prioritize multiple tasks in a dynamic environment. Proven ability to plan and prepare for customer meetings and to work with minimal supervision. Entrepreneurial mindset with a proactive, customer-focused attitude. Ability to think and act quickly while maintaining a high standard of quality. Strong cross-functional collaboration skills. Required Experience : Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications. Identify key logic components and critical micro-architectural properties essential for ensuring design correctness. Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs. Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth. Develop and maintain scripts to enhance FV productivity and streamline verification processes. Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels. Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback. Strong proficiency in System Verilog/Verilog. Good scripting abilities with Python or Perl. Preferred Experience : Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold. Experience with both bug hunting and static proof verification techniques. Familiarity with automating formal verification workflows within a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

We are hiring a strong Design Verification (DV) engineer. This opening is with our CPU Design Verification team. This role is for you if you are curious about Computer organisation and design, and possess strong digital design fundamentals. This role is with a Hardware design and verification team that develops and builds chips enabling the AI revolution. What you will be doing: You will own and develop verification components, such as checkers, models, coverage, and stimulus. You will work closely with the Architecture, RTL, and Formal Verification teams to design and verify the microarchitecture. You will propose methodology, tests and frameworks to ensure bug-free RTL. You will participate in Design specification reviews, architecture reviews, and reviews of other unit test plans. Build DV code and Algorithms that are of high quality, with excellent time and space complexity, that scale well to higher testbenches. You will actively work on understanding the ARM architecture and coherency protocols, such as CHI. You will learn the microarchitectures of the interconnect, cache, ordering, and memory units in the system. This role will enable you to develop expertise in CPU load/store, MMU, caching, coherency/consistency, fabric, and related areas. You will design and verify the next generation of NVIDIA CPUs and SoCs! What we need to see: BS or MS in Electronics Engineering with a minimum of 3+ years of proven experience Knowledge in Design Verification Methodologies SV/UVM verification languages and methodologies. Strong problem solving - more specifically, DV code like stimulus, models, constraints, coverage Prior experience in Testbench architecture and Verification components A strong understanding of CPU architecture and microarchitecture Way to stand out from the crowd: Understanding CPU Architecture concepts related to load/store, caching, coherency, consistency and ordering Strong Python and other software methodologies for scripting and build automation Experience in handling EDA tools from Synopsys or Cadence With competitive salaries and a generous benefits package, we are widely considered as one of the technology world s most desirable employers. We have some of the most dedicated and experienced professionals in the world working for us, and, due to unprecedented growth, our elite engineering teams are expanding rapidly. If youre a creative and autonomous engineer with a real passion for technology, we want to hear from you! We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, colour, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 8+ years of experience in Physical Design/Implementation Minimum Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support.Responsibilities:Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality.Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation.Minimum Qualifications:Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.8+ years ASIC design verification, or related work experience.Knowledge of a HVL methodology like SystemVerilog/UVM.Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.Preferred Qualifications:Experience with Low power design verification, Formal verification and Gate level simulation.Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value addExperience in scripting languages (Python, or Perl).

3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Deliver No.Performance ParameterMeasure1.Product design, engineering and implementationCSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards2.Capability development% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) Applications from people with disabilities are explicitly welcome.

HW Physical Design macros with Innovus and ICC2 tools. block implementation such as floorplanning, placement, clock tree synthesis, routing and optimization. signoff closure related fixes and runs ,formal verification and physical verification.

HPC is an organization responsible for Renesas business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Senior Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Staff Engineer, DV We are seeking a highly motivated and experienced Staff SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities - MCU-Level UVM Verification: Implement modular UVM testbenches for SoC subsystems (e. g. , sensor hubs, AI accelerators, communication fabrics). - Develop coverage-driven verification plans (functional, code, assertion coverage) aligned with automotive safety and security requirements. - Debug complex SoC-level scenarios (e. g. , multi-protocol interactions, power-aware verification). Automotive VIP Integration: Integrate and customize 3rd-party VIPs (e. g. , Synopsys, Cadence, Mentor) for automotive protocols. Soft Skills - Demonstrated ability to provide clear and transparent communication within teams and with global customers. - Agile mindset to adapt to dynamic project requirements and timelines. - Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. - Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

HPC is an organization responsible for Renesas business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Senior Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Sr. Staff Engineer, DV We are seeking a highly motivated and experienced Sr. Staff SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities - Safety-Centric DV: Define and execute verification plans aligned with ISO 26262, including FMEDA (Failure Modes Effects and Diagnostics Analysis) and safety mechanisms. - Develop safety-aware testbenches, assertions, and coverage models (e. g. , fault injection, safety coverage metrics). - Formal & Simulation-Based Verification: Apply formal methods to prove correctness of safety-critical logic (e. g. , redundancy, error correction). - Collaborate with cross-functional teams to validate safety requirements (e. g. , hardware diagnostics, lockstep cores). - Toolflow Leadership: Optimize toolchains for safety verification automation. - Document verification artifacts for ISO 26262 compliance audits. Soft Skills - Demonstrated ability to provide clear and transparent communication within teams and with global customers. - Agile mindset to adapt to dynamic project requirements and timelines. - Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. - Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

HPC is an organization responsible for Renesas business operations primarily focused on automotive MCUs (Microcontrollers) and SoCs (System-on-Chips). It specializes in high-performance computing technology that supports the evolution of automobiles, providing essential semiconductors for next-generation automotive systems such as advanced driver assistance systems (ADAS), connected cars, EV control, and infotainment. HPC offers diverse roles, including MCU/SoC design and development, marketing, and business management. HPC operates globally, collaborating with locations in Japan, the United States, Europe, China, India, and other countries. We are seeking a highly motivated and experienced Senior Staff SoC/MCU Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, formal verification, strong technical leadership, and excellent problem-solving skills. Sr Engineer, DV We are seeking a highly motivated and experienced Sr SoC/MCU Design Verification Engineer to join our team. In this role, you will contribute to the verification of complex System-on-Chip (SoC/MCU) designs, ensuring functionality, performance, and quality meet project and customer specifications. This position requires expertise in advanced verification methodologies, strong technical leadership, and excellent problem-solving skills. Key Responsibilities Power-Aware UVM Verification: Execute UPF-driven testbenches to validate power management features: Power gating, isolation, retention. State transitions verification and Verify low-power sequences UPF strategies for hierarchical power domains and Debug power-related failures (e.g., isolation violations, retention flop corruption). Integrate power-aware assertions and coverage metrics. SoC-Level Verification: UVM environments for multi-power-domain SoCs (e.g., processors, interconnects, peripherals). - 4+ years of Experience required. Soft Skills - Demonstrated ability to provide clear and transparent communication within teams and with global customers. - Agile mindset to adapt to dynamic project requirements and timelines. - Innovative thinker capable of contributing ideas to enhance designs or optimize workflows. - Proven ability to manage daily tasks and lead a design team with a sense of ownership and accountability. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

About the Role Skills: Strong in IP / SoC-level verification Responsibilities Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Experience: 5+ years in Design Verification Required Skills Strong in IP / SoC-level verification Proficient in testbench and testcase development (SystemVerilog/UVM preferred) Clear understanding of verification plans, coverage metrics, and debugging Availability: Immediate to within 4 weeks

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the hardworking System IP team! This is a fast-paced technical role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems! About System IP This role is for the System MMU product teams The SMMU team owns the development of next-generation Arm SMMU targeting high-end mobile, networking and enterprise markets The SMMU is a key component of the Arm Architecture that provides critical and complex functionalities that complement systems design with Arm processors and Multimedia IP What will I be accountable for You will specify and develop new hardware verification testbenches for future generation hardware IP You will improve existing testbenches to increase performance, quality and efficiency You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practises and state of the art for hardware verification The responsibilities of a member of the Verification team are Reviewing and assessing proposed design changes from a verification complexity point of view Develop and own verification plans for IP blocks based on architecture and design specifications Define testbenches, coverage goals, and verification environments using industry-standard methodologies Investigating and scripting new verification flows and optimising existing ones Developing methodology and deploying within the group and having full ownership of verification closure and mentoring other members of the team Collaborate with architects, RTL designers, and software teams to define verification scope and goals Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system Essential skills and experience You can demonstrate experience in working with constrained-random verification including ownership of a suitably complex verification environment Experience of architecting and implementing functional verification environments for complex IP Experience developing re-usable and scalable code whilst having good knowledge of UVM Strong scripting skills being able to develop scripting to support new flows Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms You are familiar with the tools and processes for developing testbenches and finishing all aspects of the verification process Strong communication skills and ability to work well as part of a team Dedicated with a focused approach to problem analysis and solving Strong experience in planning and estimation Desirable skills Team leadership and mentoring experience Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e g AMBA5 CHI, AMBA4 ACE or AXI) Experience in Formal Verification testbenches is a plus Core Beliefs The opportunities ahead of us are immense To seize these opportunities, speed, efficiency and impact matter We need to work fast, make decisions quickly, be nimble and efficient, and operate as one Arm rather than in siloed teams thinking solution and product first At Arm, we aim to live fully the following three Core Beliefs 'Do great things' means we work with urgency, embrace challenges, find a way 'We, not I' means we embrace both collaboration and individual accountability for the success of Arm 'Be your brilliant self' mean we insist on excellence and we enable performance, individuality and inclusion across Arm Arm is committed to global talent acquisition, offering an attractive relocation package With offices around the world, Arm is a diverse organisation of dedicated, creative and highly talented engineers By enabling a dynamic, inclusive, meritocratic, and open workplace, where all our people can grow and succeed, we encourage our people to share their unrivalled contributions to Arm's success in the global marketplace We are an Equal Opportunity Employer, value diversity at our company and do not discriminate against any employee or applicant for employment on the basis of race, colour, gender, age, national origin, religion, sexual orientation, gender identity, status as a veteran, and basis of disability or any other federal, state or local protected class Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm com To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: The candidate will be responsible for working in the formal verification domain, specifically targeting designer applications within JasperGold. Additionally, the candidate will contribute to machine learning initiatives into designer apps. Candidate should have 1 -2 years of experience and be proficient in C++ with a strong understanding of data structures and algorithms. Knowledge of Verilog, VHDL and Qt is a plus. We re doing work that matters. Help us solve what others can t.

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Questa Simulation Product It is a core R&D team working on multiple verticals of Simulation. A very energetic and enthusiastic team of motivated individuals. This role is based in Noida. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We make real what matters! Key Responsibilities: We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 4+ years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday #LI-EDA #LI-Hybrid #DVT