MIPS

Office Admin Prepare RFQ CRM customization and data entry Expert in Migrating data from Internet to Excel and SAP Expert in Excel Expert in Windows /MS Outlook Shall have Very Good English Reading and Writing skills Job Type: Full-time Pay: ₹15,000.00 - ₹18,000.00 per month Schedule: Day shift Supplemental Pay: Yearly bonus Ability to commute/relocate: Thrissur, Trichur - 680001, Kerala: Reliably commute or planning to relocate before starting work (Required) Experience: Microsoft Office: 1 year (Preferred) total work: 1 year (Preferred) Application Deadline: 30/06/2025 Expected Start Date: 01/07/2025

Embedded Software Engineer – RTOS & Post-Silicon Validation About The Role Join the RISC-V Revolution! We are looking for talented Embedded Software Engineers to join our Automotive MCU Platform Team, with a focus on RTOS-based Software Development and Application Verification & Validation (AVV). You will be part of a growing team building MIPS’ RISC-V-based real-time processors and their associated software stack – shaping the future of embedded control systems for automotive applications like EVs, ADAS, powertrain, and domain controllers. This is a unique opportunity to contribute across the full silicon-to-software lifecycle, combining software engineering with post-silicon validation to ensure high-quality, safety-critical SoC solutions. What We Offer At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting-edge applications with industry-leading customers. Responsibilities Develop embedded software components for RTOS-based SDKs, including Low-Level Drivers (LLDs), HALs, RTOS abstraction layers, and BSPs. Develop example, demo applications to showcase peripheral functionality and performance. Support post-silicon validation (AVV) by creating validation test apps that reuse RTOS SDK components. Bring up first silicon and validate critical peripherals (ADC, PWM, CAN, LIN, watchdogs, etc.). Support automation of lab and CI-based test execution. Collaborate across teams – work closely with architecture, hardware, safety, and tools teams to align software with silicon capabilities and roadmap. Contribute to reference software and tooling to aid customers in bootstrapping their own designs. Analyze and debug complex issues using emulators, silicon, and debug tools like OpenOCD, J-Link, or Lauterbach. Provide feedback into next-gen MCU architecture, based on software validation findings. Contribute to the wider RISC-V software ecosystem, helping to ensure support for the architecture in various open-source projects. Qualifications 3–8 years of hands-on experience in embedded systems software development. Strong skills in C, C++ programming, with basic familiarity in assembly. Good understanding of RTOS concepts (task scheduling, ISRs, semaphores, etc.). Experience debugging complex multicore systems, experience with debugging tools (OpenOCD, Segger J-Link, Lauterbach). Experience porting or developing on FreeRTOS, Zephyr, AUTOSAR OS, or similar platforms. Familiarity with bare-metal development, memory-mapped IO, and driver development. Experience in bring-up and debugging on real silicon or FPGA platforms. Knowledge of automotive interfaces and protocols CAN, LIN, SPI, I2C, UART. Practical exposure to test automation, scripting (Python, bash), and version control (git). Bonus Points Exposure to ASIL-D software development, ISO 26262 process, or safety validation. Prior involvement in post-silicon AVV or hardware-in-the-loop (HIL) test setups. Familiarity with RISC-V architecture, instruction sets, and toolchains. Experience developing or validating motor control, powertrain, or safety-critical firmware. Knowledge of bootloaders, secure update, or system startup firmware. Benefits Opportunity to work on cutting-edge RISC-V platforms with real industry adoption. A fast-paced, engineering-driven environment with minimal red tape. Mentorship from veteran CPU and embedded software engineers. Direct involvement in building safety-critical systems from the ground up. Exposure to a full-stack SoC development lifecycle from pre-silicon to production-ready. Flexible growth path – whether you want to specialize deeply or lead in the future. About MIPS MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power-efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products – the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V-based solutions.

Embedded Software Design Internshipbody { font-family: sans-serif; text-align: justify; }p { margin-bottom: 1em; }b { font-weight: bold; }ul { list-style-type: disc; margin-left: 20px; } Embedded Software Design Internship Job Description 6-month, 1-year internship opportunities in Embedded Software Design at MIPS.2026 or later Graduates (2025 graduates not qualified) Requirements Master`s or Bachelor`s degree in Electronics Engineering, Electronics and Telecommunication Engineering, Computer Science, Electrical Engineering. Strong academic track record (CGPA 8.0+ preferred) Responsibilities Work on firmware, RTOS (FreeRTOS, Linux), and device drivers for high-performance processors and microcontrollers. Skills Embedded C, OS fundamentals, RTOS, Linux Computer Architecture knowledge a must Bonus: AI, ML or networking stack experience

As an intern in the SOC design team at MIPS, you will have the opportunity to be part of a 6-month or 1-year program. Candidates who have graduated in 2026 or later are eligible to apply, with 2025 graduates not meeting the qualification criteria. To be considered for this internship, you should possess a Master's or Bachelor's degree in Electronics Engineering, Electronics and Telecommunication Engineering, Computer Science, or Electrical Engineering. A strong academic track record with a CGPA of 8.0 or higher is preferred. The internship positions are available in Pune and Bangalore. Your main responsibilities will include designing and integrating subsystems into SoCs and contributing to the definition of RTL development flows for MIPS RISC-V processors. The key skills required for this role include proficiency in Verilog, SystemVerilog, VCS, Verdi, as well as strong scripting abilities in languages such as Tcl, Python, and Perl. Additionally, strong debugging skills will be beneficial in carrying out your day-to-day tasks effectively.,

The Embedded Software Design Internship at MIPS offers 6-month to 1-year opportunities for graduates from the year 2026 onwards. As an intern in this role, you will be responsible for working on firmware, real-time operating systems (RTOS) such as FreeRTOS and Linux, as well as device drivers for high-performance processors and microcontrollers. To qualify for this internship, you must hold a Master's or Bachelor's degree in Electronics Engineering, Electronics and Telecommunication Engineering, Computer Science, or Electrical Engineering. A strong academic track record with a CGPA of 8.0 or above is preferred. The key skills required for this role include proficiency in Embedded C, a solid understanding of OS fundamentals, RTOS, and Linux. Additionally, knowledge of computer architecture is essential. Experience in AI, ML, or networking stack would be considered a bonus. If you are passionate about embedded software design and possess the necessary qualifications and skills, this internship at MIPS could be the perfect opportunity for you to gain hands-on experience in a dynamic and innovative work environment.,

About The Role We are seeking a highly skilled Full Stack Software Engineer to join our team and help us build the next-generation Engagement Portal for our customers. In this role, you will be involved in various aspects of web application development, including frontend user interfaces, backend APIs, database design, authentication systems, real-time collaboration tools, visualization platforms, simulation integration, and performance dashboards. You will work directly with customers at all stages, including onboarding, support, and requirements gathering. This is an exciting opportunity to work in a dynamic environment, involving interaction with our engineering teams, including hardware validation, architecture, design, and software as we build both front-end and back-end systems from the ground up! Our Mission Our aim is to build applications that not only allow our silicon designs to be validated but also provide our customers and partners with a robust platform to kick-start their evaluation of Silicon, allowing them to obtain the highest confidence from design and validation. We are committed to offering "Freedom to Innovate Compute". More About Us MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products, the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions. At MIPS, you will be a member of a fast-growing team of technologists that are creating the industry`s highest performance RISC-V processors. At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave! Responsibilities Frontend development and interactive design visualization interfaces Backend API development and other relevant frameworks on cloud and containerized environments Deploying pre-existing validation workflows like simulation result visualization or developing new ones as per customer needs Contribute to the wider silicon validation software ecosystem, helping to ensure support for the platform in various open-source design tools Use tools and real user feedback to analyze and optimize applications, including through the use of performance monitoring and user experience improvements Code-review complex frontend and backend contributions in any of these areas Interact with hardware validation and design teams to improve our next silicon validation platform – provide inputs and drive architectural decisions based on user experience needs Help maintain the documentation and reference implementations that our customers rely on Release platform APIs and work with customers to enable integration of their validation workflows for evaluation and development Ideal Candidate Qualifications Experience with full-stack web development Strong JavaScript, TypeScript, or Python programming experience, basic SQL database programming Knowledge of basic web application concepts (e.g., REST APIs, authentication, state management, responsive design) Experience developing user interfaces or backend services in modern frameworks and cloud platforms Proven experience with frontend frameworks (React, Vue.js, Angular, etc.) on different deployment architectures Experience debugging complex web applications Experience with Git, npm, yarn, CI,CD pipelines, and deployment automation scripting Experience with databases, caching, microservices, authentication systems, and application security Experience working with hardware validation and engineering teams Strong communication, collaboration, and listening skills Additional Skills (Nice To Have) Familiarity with silicon design workflows. Knowledge of different EDA tools (e.g., Synopsys, Cadence, Mentor Graphics) Experience working with data visualization and charting libraries (D3.js, Chart.js, Plotly) Some experience working with real-time applications (e.g., WebSockets, real-time collaboration, or streaming data) Any experience with simulation integration or hardware validation automation, FPGA-based validation environments would be very interesting for us

We are looking for an experienced Staff Design Engineer CPU RTL to take on the responsibility of leading and owning RTL development for one or more modules of a high-performance CPU core. Your role will encompass all facets of the design, including Performance, Power, and Area. In this position, you will be expected to drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core. You will work closely with the CPU modeling team to explore high-performance strategies. Your responsibilities will also include developing microarchitecture and specifications, configuring design features, and refining RTL design to meet power, performance, area, and timing objectives. Additionally, you will provide support for functional verification and assist in defining the design verification strategy. Collaborating with a multi-functional engineering team, you will help implement and validate physical design aspects related to timing, area, reliability, testability, and power. To qualify for this role, you must have hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core. A thorough understanding of microprocessor architecture is essential, particularly in areas such as Instruction fetch and decode, branch prediction, Instruction scheduling, register renaming, Out-of-order execution, Integer and Floating-point execution, Load, Store execution, prefetching, Cache, and memory subsystems. Proficiency in Verilog and/or VHDL, experience with simulators and waveform debugging tools, and knowledge of logic design principles are required. Ideally, you should hold a Masters degree with 5-8 years of experience or a PhD with 3-4 years of work experience. Candidates with experience in designing RISC-V, ARM, and/or MIPS CPUs, hardware multi-threading, virtualization, and SIMD designs will be given bonus points. Familiarity with high-performance and low-power microarchitecture techniques, as well as expertise in using scripting languages like Perl or Python, is advantageous. At MIPS, you will be joining a dynamic team of technologists dedicated to developing the industry's highest performance RISC-V processors. You will have the opportunity to work in small teams within a non-compartmentalized structure, offering autonomy and the chance to contribute to the bigger picture. With support from experienced CPU engineers, you can chart your own growth path within the organization. Additionally, you will gain valuable insights into the RISC-V architecture and its applications by working with industry-leading customers. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave for employees and their families. MIPS is recognized as a pioneer in microprocessor technology, with a legacy of leading RISC-based computing for various applications. Building on over 30 years of expertise, MIPS is at the forefront of the RISC-V revolution, focusing on developing high-performance processors like the MIPS eVocore series. As a part of the MIPS team, you will play a key role in accelerating the adoption of RISC-V solutions with cutting-edge technologies and deep engineering knowledge.,

MIPS is looking for a highly experienced and motivated Engineering Manager to lead the CPU team. In this critical role, you will manage a team of skilled engineers dedicated to developing high-performance CPU cores based on the RISC-V architecture. Your responsibilities will include overseeing the entire RTL design lifecycle, ensuring technical excellence, innovation, and timely delivery. You will lead and mentor a team of microarchitecture and RTL design engineers focused on high-performance CPU core development. Your role will involve driving the design execution of CPU subsystems, meeting performance, power, area, and quality goals. You will be responsible for creating and refining microarchitecture specifications and RTL designs for CPU core components, collaborating with various teams to ensure efficient implementation, optimizing design methodologies for scalability and quality, and fostering a culture of innovation and technical excellence. The ideal candidate should have a Master's or PhD in Electrical Engineering, Computer Engineering, or a related field, with at least 15 years of experience in silicon or CPU design, including 5+ years in a management role. A proven track record of successfully delivering complex CPU blocks or subsystems, deep understanding of microprocessor design principles, strong technical knowledge in RTL design, and experience with project management and organizational skills are required. Preferred qualifications include experience with RISC-V, MIPS, or ARM CPU cores, familiarity with advanced CPU design concepts, working in a globally distributed environment, proficiency with EDA tools and scripting languages, and modern design methodologies. Joining MIPS offers you the opportunity to work with a dynamic and fast-growing team that is shaping the future of high-performance RISC-V processors. With small, agile teams and a flat organizational structure, you will have a direct impact on cutting-edge technology and product direction. MIPS provides an autonomous and empowering work culture, the chance to collaborate with industry-leading engineers, competitive compensation and benefits, and a platform for career growth in the exciting RISC-V ecosystem.,

Join the RISC-V Revolution! As a highly skilled FPGA and emulation engineer lead at MIPS, you will play a crucial role in building FPGA designs for our CPU`s (64-bit and 32-bit) and SOCs. Your responsibilities will include designing, building, and developing innovative FPGA and emulation platform solutions, performing pre-silicon CPU and system validation, analyzing system performance, and creating tailored FPGA prototyping platforms. You will collaborate closely with customer teams and provide technical support for FPGA systems in various contexts. In this role, you will have the opportunity to contribute across the full silicon-to-software lifecycle, combining software engineering with post-silicon validation to ensure high-quality, safety-critical SoC solutions. You will work with small teams in a non-compartmentalized structure, enabling you to understand the bigger picture and have a significant impact. You will receive support from experienced CPU engineers, have autonomy in your work, and enjoy an unlimited growth path based on your skills and interests. Ideally, you will have 10+ years of hands-on experience with leading FPGA platforms such as proFPGA, VPS, and Veloce. You should possess a solid understanding of FPGA architecture, system-level design, prototyping flow, verification, and validation fundamentals. Experience with integrating and bringing up daughter cards, custom IP blocks, and peripherals is essential. Familiarity with SoC boot flows, platform initialization, MIPS, ARM, or RISC-V based IP subsystems, and debugging skills in Windows and Linux environments are desired qualifications. Additionally, experience working on CPUs, familiarity with different Instruction Set Architectures, hardware-software co-design, agile tools, and strong communication skills will be advantageous. MIPS, a microprocessor pioneer, is leading a RISC revolution by accelerating the RISC-V architecture for high-performance applications with the MIPS eVocore processors. Join us to be part of this exciting journey and contribute to cutting-edge applications with industry-leading customers.,

You will be joining MIPS, a leading provider of configurable and efficient compute solutions for the automotive, cloud, and embedded markets. With a strong emphasis on accelerating compute density, MIPS" industry-leading cores offer advanced scalability and efficient data processing capabilities. With a rich history spanning over two decades and billions of MIPS-based chips shipped, the company stands at the forefront of innovation in the compute industry. As a Senior Technical Leader - RTOS SDK & Post-Silicon Validation at MIPS in Pune, your primary responsibility will be to spearhead technical initiatives concerning Real-Time Operating System (RTOS) Software Development Kit (SDK) and post-silicon validation. This full-time on-site role will involve overseeing the development of RTOS SDK, designing and implementing post-silicon validation tests, and ensuring the quality of the end product. To excel in this role, you should possess experience in Real-Time Operating System (RTOS) development, along with proficiency in SDK development and post-silicon validation. Strong problem-solving and debugging skills are essential, as well as a solid understanding of embedded systems and microcontrollers. Your leadership and communication skills will play a crucial role in driving technical initiatives forward. Ideally, you should hold a Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field. Previous experience in automotive or cloud computing industries would be advantageous. Join us at MIPS and be a part of a dynamic team that is shaping the future of compute solutions.,

As an Office Admin, your responsibilities will include preparing Request for Quotation (RFQ), customizing CRM systems, performing data entry tasks, and migrating data from the internet to Excel and SAP. You should be an expert in Excel, Windows, and MS Outlook. Additionally, you should possess very good English reading and writing skills. This is a full-time position with day shift schedule and a yearly bonus. The ability to commute to Thrissur, Trichur - 680001, Kerala is required, or you should be planning to relocate before starting work. The ideal candidate should have at least 1 year of experience in Microsoft Office and a total of 1 year of work experience. The application deadline for this position is 30/06/2025, and the expected start date is 01/07/2025.,

The Physical Design Manager role at MIPS involves leading and guiding teams in the creation of custom integrated circuits (ICs) to meet specific customer requirements. You will oversee the entire physical design process, from synthesis to verification, ensuring project efficiency, quality, and innovation. Your responsibilities will include managing a team of physical design engineers, developing design strategies, maintaining re-use methodologies, and collaborating with cross-functional teams and customers to deliver optimized solutions. You should have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with at least 5 years of experience in managing physical design teams and technical expertise in the field. Proficiency in RTL to GDSII flows, physical synthesis, PNR, STA, and physical verification methodologies is essential, along with hands-on experience with industry-standard EDA tools. Strong leadership, project management, and communication skills are required to excel in this role. The ideal candidate for this position is a strategic thinker with experience in delivering custom silicon solutions and mentoring high-performing teams. You should be customer-focused, proactive in solving technical challenges, and passionate about continuous learning and implementing industry best practices. Additionally, you will have the opportunity to work with a fast-growing team of technologists at MIPS, creating high-performance RISC-V processors and contributing to the development of cutting-edge applications.,