RTL Design Intern

As an intern in the SOC design team at MIPS, you will have the opportunity to be part of a 6-month or 1-year program. Candidates who have graduated in 2026 or later are eligible to apply, with 2025 graduates not meeting the qualification criteria. To be considered for this internship, you should possess a Master's or Bachelor's degree in Electronics Engineering, Electronics and Telecommunication Engineering, Computer Science, or Electrical Engineering. A strong academic track record with a CGPA of 8.0 or higher is preferred. The internship positions are available in Pune and Bangalore. Your main responsibilities will include designing and integrating subsystems into SoCs and contributing to the definition of RTL development flows for MIPS RISC-V processors. The key skills required for this role include proficiency in Verilog, SystemVerilog, VCS, Verdi, as well as strong scripting abilities in languages such as Tcl, Python, and Perl. Additionally, strong debugging skills will be beneficial in carrying out your day-to-day tasks effectively.,