14 Verdi Jobs

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. Join QCOM Technologies Inc Global Emulation(Prototyping) team delivering solutions for design of leading-edge wireless products. Qualcomm is leading 5G innovations ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. The Qualcomm Global emulation team is currently seeking a lead engineer role for our team doing development/validation of large scale FPGA emulation tools/flows/methodologies In this role, you will be working in multiple areas of SoC/IP prototyping flows and methodologies. Would also involve enabling execution teams doing SOC prototyping during their usage of the platform Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 4-7 years of experience working in FPGA Synthesis, Prototyping of SoCs & IPs Candidates are expected to have experience in: Prior work experience on Emulation/Prototyping Platforms (HAPS, VPS, Protium etc) Multi-FPGA prototyping flow, from RTL preparation to h/w implementation Proficient in analysis & debug of issue in Synthesis, Place and Route, Timing closure, Clocking. Hands on experience in FPGA h/w debug using probes/ILA Proficient in EDA tools like - Vivado, Synplify, Protocompiler, VPS, VCS/Verdi etc RTL coding and simulation Well versed with working in unix/linux environment, using GVIM/VI editors, shell scripting Strong debug skills, aptitude to learn and resolve complex issues Experience in one or more scripting language - TCL, Python, Perl, Shell etc Sound knowledge of: FPGA architecture preferably Xilinx (ultrascale), Vivado IP catalog Synthesis, Timing concepts and SDC constraints Prototyping concepts like - partitioning, pinmux

Emulation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: should have emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput tuning Experience using Verilog, VHDL design Experience with C/C++ and System Verilog, UVM verification environments Experience writing scripts using Perl, Python, Makefile Debugging experience using tools like waveform, Verdi, Simvision Strong communication skills and ability to work as a team Description You’ll support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). You’ll be bringing up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. – We are in constant collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. – Your strong design, debug, communication, and teamwork skills will be essential. – You will also work with leading emulation vendors to debug issues. Skills Experience Zebu Verilog, Python Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity and manufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus. Knowledge of any high-speed communication protocol is not mandatory but an asset. Previous knowledge in customer support and/or silicon bring-up is a plus. The Impact You Will Have: Strengthen and develop forecasting capabilities based on improved monitoring capacity. Ensure high-quality and reliable silicon lifecycle monitoring solutions. Enhance quality assurance methodology by adding more quality checks/gatings. Support internal tools development and automation to improve productivity across ASIC design cycles. Work with design engineers on new tools/technology and new features evaluation and adoption. Contribute to the successful and smooth operation of the engineering teams. What You'll Need: Bachelor's or master's degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency in industry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, and methodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design.

Your Impact Develop test plans, cover points, and qualification tests Perform end-to-end verification of design blocks and top-level Build and maintain block, cluster, and top-level DV environment infrastructure Construct testbenches components like scoreboard, agents, sequencers, and monitors Write tests, debug regressions, and drive to module verification closure Collaborate with designers and verification engineers for cross-block verification Upgrade configuration/reset sequences (APIs) Develop environment and tests for emulation Ensure complete verification coverage through code, functional coverage, and gate level simulations Support post-silicon bring-up and optimize integration and performance Minimum Qualifications Bachelors Degree in EE, CE, or other related fields with 6+ years or Masters Degree with 4+ years of ASIC design or verification experience Experience in developing verification environment for complex blocks from design specifications document Proficient in verifying complex blocks and/or clusters for ASIC using UVM/System Verilog. Scripting experience with Perl, Python, TCL, shell scripts. Preferred Qualifications Experience in Data center/ Hyper scaler /AI Networking technologies Proven experience meeting and delivering project milestones and deadlines. Ability to communicate technical concepts to audiences spanning executives to junior engineers to customers. Demonstrated ability in troubleshooting and debugging. Experience with Emulation and Formal Verification tools is a plus.

About The Role Solid Experience in DFT Architecture. The candidate should have experience with ATPG, JTAG, BSCAN, BIST and MBIST flows. Experience on Hierarchical DFT techniques using Pattern Retargeting in Tessent flow Strong knowledge of the Tessent Shell environment and Tessent tools The desired candidate must have specific emphasis on the following tools Test Kompress / Fastscan ATPG, MBIST, Boundary scan. Hands on experience in simulating scan patterns and debugging pattern mismatches during verification process Experience in helping to debug failing scan patterns on the ATE is highly desirable. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Must be able to simulate and debug MBIST testbenches. Ability to come up with a detailed test plan based on the Arch specs Should be knowledgeable in all SOC functions such as Digital design, STA, Synthesis, PnR, DV and ATE test. The candidate should have prior experience in managing and developing teams Required Qualification B.E / B.Tech / M.E / M.Tech in Electrical / Electronic Engineering. experience-10-16 years Preferred experience of handling 10+ team members. Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Comfortable with VCS / Verdi and excellent debugging skills Logical in thinking and ability to gel well within a team and be a proactive member of the team. Good communication and leadership skills Excellent team player High Integrity Job Type Full Time Job Location Hubballi

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 10+ years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s custom silicon/ASIC designs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES : Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to understand Architecture and verification asks Ability to come with detailed testplan based on the Arch specs Good understanding and exposure to SoC design and architecture 4years of Design Verification experience with strong Verilog, System Verilog, C and UVM/OVM knowledge Candidate should be able to develop Testbench. Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects. Developing functional coverage & assertions. Own the DV sign-off and ensure a bug free design Work with the post-silicon team on debug support and to help root-cause any failures Have worked on wireless protocol design verification Bringing up Testbench/SoC verification environment. Good understanding of SoC RESET/CLOCK flow Exposure to DEBUG concepts such as JTAG etc Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team Good communication skills PREFERRED EXPERIENCE: Proficient in SoC/sub-system/IP level ASIC verification Proficient in debugging RTL code using simulation tools Experienced with Verilog, System Verilog, C, and C++ Worked on any High Speed Interface like PCIE/DDR/USB/Other, Good understanding of AXI/AHB/APB Bus protocol Prior knowledge of ARM/RISC Processor based designs verification and bring-up verification Developing UVM based verification frameworks and testbenches, processes and flows Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred.

Be a member of the team that plays a significant role in ensuring the quality of next generation microprocessors through structured DFT. 5+ years of Design Verification experience with strong Verilog, System Verilog, C++ and UVM/OVM knowledge Good understanding and exposure to SoC design and architecture Thorough understanding of verification environments including need, methodology, stimulus, checkers, scoreboards, coverage aspects Ability to come with detailed testplan based on the Arch specs Exposure to DFT concepts such as JTAG, SCAN, memory BIST is an added advantage. Comfortable with VCS/Verdi and excellent debug skills Logical in thinking and ability to gel well within a team and be a proactive member of the team.

About The Role : You will be part of world class Intel Emulation Solutions team (ES) team responsible for driving the Emulation strategy across Intel's next generation products. ES team is leading the innovations and new technologies with Virtual Platform/Emulation/Hybrid solutions partnering with Intel teams as well external EDA vendors accelerating Intel product TTM. In this role you will be responsible for defining and developing new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation model usability for preSilicon and postSilicon functional validation as well as SW development/validation. You will also develop improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. You will interface with and provide guidance to preSilicon Validation teams for optimizing preSilicon validation environments, test suites and methodologies for emulation efficiency. You will be responsible for developing and applying automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. Qualifications Must have a Bachelor's degree or Master's degree in Electrical, Electronics or Computer Engineering with relevant experience of at least 3+ years Experience with emulators such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce for large scale designs Strong understanding of Computer architecture, design principles, validation methodologies and tools Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based verification techniques. Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments. Experience in SW Programming/scripting and debug such as assembly, C, C++, Perl, Python Prior expertise in CPU, Coherency, reset, Global Flows, Power management, memory, PCIe highly desirable Prior experience in System Validation is a plus. Must possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Spec: Understand Video Codec specification for respective blocks Micro-architect of sub-block design Understand all interfaces/Config for respective blocks Coding and debugging the functionality for all respective blocks Perform design optimizations for Power/Area/Timing/Performance Skillset looking for: Strong DSP/Multimedia Domain Knowledge on Video Codecs/Computer Vision along with Hardware Implementation is preferred. Experience in micro-architecting & designing complex datapath cores for ASICs/SoCs including AI/ML cores for CV applications Experience with RTL coding using Verilog/VHDL/system Verilog Familiar with the Synthesis and Formal Verification Simulation debugging with Verdi & log file. Exposure in scripting Familiar with the Linting, CDC, Low Power etc. Good team player. Need to interact with the verification engineers proactively Ability to debug and solve issues independently Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm.Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities As a Design Automation Engineer, you will work with RTL, architecture, design, DV, software, and silicon verification users. Develops, maintains, debugs and tests CPU Design Methodologies using Commercial EDA tools Defines and creates flows/scripts to help design teams execute Front-End (RTL) flows seamlessly Create unit, integration, regression, and/or system-level tests to thoroughly validate new features or changes. Work closely with Eng IT teams to setup flows which work well with the Engineering Compute Infra at multiple Datacenters Work closely with design teams to define methodologies, drive flow development, and deploy vendor tools Interfaces with external vendors to define, drive and incorporate the latest design solutions to improve productivity and time to market. Support design engineers on the flow setup and resolve their queries, automate tasks through appropriate tools and scripting. Review and debug code to identify and fix code problems. Qualifications Proficient with Python development and strong working knowledge of Linux operating systems Must have worked on Digital flows/methodologies development in the DV domains. Should have proficient skills with one of DV related tools Xcelium/VCS/vManager/Indago/Verdi or equivalent. Experience with CI/CD platform (like Airflow and Jenkins) and Version Control System (like Perforce and/or Git). MS/BS in Electrical/Computer Engineering with 8-14 years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Demonstrated experience with various EDA software, flows, and architectures & driving EDA vendors to provide feature enhancements and bugfixes. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. KEY RESPONSIBILITIES: Define and develop DFT feature verification requirements and test plans for current and next generation products Build comprehensive validation infrastructure including test bench components, agents, monitors, checkers, scoreboards Construct System Verilog and test sequences for comprehensive feature simulation, evaluate feature coverage and regression health Participate in methodology development to increase verification efficiency and effectiveness. PREFERRED EXPERIENCE: 8+ years of VLSI Design and DFT testability Deep understanding of VLSI DFx strategies (ex. JTAG, BIST, ATPG, Boundary Scan) Excellent scripting skills (ex. Perl, C shell, Python). Proficient in debugging RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Strong experience with Verilog, System Verilog, C, and C++ Working knowledge with EDA simulation tools including Synopsys VCS, Cadence NCSIM, Verdi Experience with UVM, OVM or equivalent Experience with formal verification techniques and industry tools Working knowledge of Unix/Linux OS and debug tools Strong analytical skills and attention to detail Excellent written and verbal communication Strong interpersonal skills and proven leadership Applicants :Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies :Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advantage. Knowledge of tensilica Worked with sub-system verification with tensilica Experience in C based system modelling. Debug with C based reference model. Have exposure to the other verification tasks :gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation. Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.