68 Vcs Jobs

You will be part of our Hardware team as a Hardware Verification Engineer, working on the development of cutting-edge custom hardware for Quantum computers. Your responsibilities will include creating models and test plans to verify the functionality and performance of our in-house chip designs. You will need to understand the design, define verification scope, develop verification infrastructure, and ensure the correctness of the design. To qualify for this role, you should have a BS or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Advanced degrees such as MS or PhD are a plus. You should have at least 3 years of relevant work experience and proficiency in verification languages like System Verilog or equivalent, along with methodologies such as UVM or equivalent. Experience with verification tools like VCS and Verdi, as well as strong debugging and problem-solving skills, are also required. If you are a motivated individual with a deep understanding of how complex SOC and IPs are built, have knowledge of client requirements, and are familiar with various development cycles, then this opportunity is perfect for you. Join us in creating the next generation of revolutionary hardware for Quantum computers. Skills required for this role include verification languages, hardware verification, verification tools like Verdi and VCS, and experience in quantum verification methodologies.,

As a Team Leader in FPGA IP Verification, you will be responsible for leading and mentoring a team of engineers. You will define team priorities, set goals, and monitor performance through KPIs and regular reviews. Your role will involve fostering an environment of learning, collaboration, and technical excellence to enhance verification efficiencies. In terms of Technical Management, you will oversee the development and delivery of verification of IPs owned by the team, ensuring alignment with QPDS/releases. You will drive innovation in verification methodologies to enhance quality and efficiency. Collaboration with FPGA design, software, and validation teams to integrate IP into the Quartus ecosystem will be a key aspect of your responsibilities. Ensuring robust quality for the IP owned and providing technical guidance on verification methodology will also be part of your role. Your Functional Expertise will involve being a hands-on technical verification lead, owning the verification of IPs for FPGA. You will perform functional logic verification of an FPGA to ensure it meets specification requirements. Developing verification plans, test benches, and the verification environment to ensure coverage confirming to microarchitecture specifications will be crucial. Executing verification plans, defining and running simulation models, uncovering bugs, and replicating, root causing, and debugging issues in the pre-silicon environment will also be part of your duties. Additionally, collaborating with various teams and documenting test plans will be essential. Qualifications required for this role include a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. You should have 10+ years of experience in verification in IP/FPGA/SoC/ASIC domains and proven expertise in RTL design and verification for FPGA architectures. Hands-on experience with OVM/UVM, System Verilog, and constrained random verification methodologies is necessary. Familiarity with simulation tools such as ModelSim, Questa, VCS, or similar EDA simulators is essential. Experience with Ethernet/PCIe/PIPE & FPGA architecture is an added advantage. In terms of Leadership & Soft Skills, you should possess the ability to lead and develop technical teams, drive collaboration, and deliver results. Strong problem-solving and analytical skills with a proactive mindset are crucial. Excellent communication and stakeholder management skills, capable of engaging both technical and non-technical audiences, will be required. This job requires a proactive individual with strong technical skills, leadership capabilities, and excellent communication abilities. If you are passionate about leading a team in FPGA IP verification and driving technical excellence, this role could be the perfect fit for you.,

About SiFive SiFive is at the forefront of introducing RISC-V to the global landscape, revolutionizing the future of computing by harnessing the boundless potential of RISC-V for the most high-performance and data-intensive applications worldwide. SiFive's unparalleled computing platforms are empowering leading technology firms across diverse market segments such as artificial intelligence, machine learning, automotive, data center, mobile, and consumer electronics to innovate and deliver cutting-edge solutions. With SiFive, the horizon of possibilities with RISC-V knows no bounds. At SiFive, we are enthusiastic about engaging with individuals who share our zeal for driving innovation and making a difference in the world. Our continuous innovation and sustained success stem from our exceptional teams of highly talented individuals who collaborate and support each other to conceive truly revolutionary ideas and solutions. These solutions are poised to significantly impact people's lives, contributing to making the world a better place, one processor at a time. Are you prepared for the challenge To delve deeper into SiFive's remarkable accomplishments and discover why we have been honored with the GSAs prestigious Most Respected Private Company Award (for the fourth consecutive time!), please explore our website and Glassdoor pages. Role: As a UPF power engineer at SiFive, you will collaborate with the Power Management Architect on feasibility studies. Your key responsibilities will include driving UPF methodology across frontend and backend teams for power intent and verification. Additionally, you will be tasked with supporting customers on UPF-related queries, collaborating with Platform engineering teams to devise scalable solutions for various design configurations. Responsibilities: - Drive UPF/CPF implementation, power/voltage domains, and power gating methodologies while working closely with the power management team. - Participate in low power design, drafting UPF, and verifying power intent at the chip level. - Engage in ASIC design flows and methodologies encompassing RTL, verification, synthesis, and static timing analysis (STA). - Collaborate with EDA vendors and tools team to establish new power methodologies, automate UPF generation, and conduct low power analysis. Required Skills: - Possess 2+ years of relevant experience. - Proficiency in Synopsys Verdi, Verdi UPF, and synthesis UPF. - Experience with power-aware simulations such as VCS/NLP or equivalent. - Familiarity with low power design implementation including UPF/CPF, multi-voltage domains, and power gating. - Knowledge of power intent definition, implementation, and verification flows. - Comprehensive understanding of ASIC design flows and IP design flows. - Strong scripting and programming skills in Python, Perl, or TCL languages. - Acquainted with power analysis and optimization methods. In this position, you will be required to undergo successful background and reference checks and provide satisfactory proof of your eligibility to work in India. Any offer of employment is subject to the Company's verification of your authorization for access to export-controlled technology under applicable export control laws or, when necessary, the successful acquisition of any essential export license(s) or approvals. SiFive is an equal opportunity employer. We value diversity and are dedicated to fostering an inclusive environment for all our employees.,

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NCSim, or Xcelium in GUI mode. Working with fault models including Stuck-at Faults and Transition Delay Faults (TDF) will be part of your role. You will also be responsible for optimizing and improving scan test coverage using established DFT techniques. The required skills and experience for this position include 5+ years of relevant experience in DFT, hands-on expertise with tools from Cadence, Siemens Tessent, and Synopsys, proficiency in debugging and analysis using VCS, NCSim, or Xcelium, strong analytical and problem-solving skills, and good communication and collaboration skills. Preferred qualifications for this role include experience in DFT automation using scripting languages like TCL, Perl, or Python, and prior exposure to automotive, networking, or high-performance computing SoCs is considered a plus.,

AppsForBharat, a Series B funded faith-tech startup, is backed by India s leading VCs including Fundamentum, Susquehanna Asia VC, Peak XV Partners (prev. Sequoia Capital), Elevation Capital, and BEENEXT. Our mission is to build digital platforms that fulfill the devotional and spiritual needs of hundreds of millions of users in India and globally. Our flagship product, Sri Mandir , is the world s largest app for Hindu devotees. With over 20 25% month-on-month growth, the app enables users to engage in spiritual practices, access sacred content, and connect with temples and rituals in a deeply meaningful way. India s devotion economy is a $44B market with immense potential for innovation. AppsForBharat is at the forefront of this transformation, creating deeply immersive spiritual experiences for users. Role Requirement We re looking for a Telugu Content Writer Intern with a proficiency in Telugu language writing along with English Language and passionate about South Indian mythological culture. If you re fluent in Telugu and English, deeply understand the traditions of the Telugu community, and want to craft meaningful content for millions of users, this role is for you. Key Responsibilities Write and translate detailed website content pieces in both Telugu and English under the supervision of the lead Telugu writer. Conduct quality checks (QC) for all website content before publishing. Manage the workflow from Level-2 writing to website live , ensuring accuracy and timeliness. Collaborate with the South vertical team within the Puja Category to ensure cultural authenticity and consistency. Requirements Proficiency in Telugu reading, writing, and grammar (mandatory). Strong command of English for accurate translations and content flow. Knowing Kannada language (writing/understanding) is a plus. Deep understanding of the religious and cultural context of the Telugu community . Organised, detail-oriented, and committed to delivering high-quality content. What We Offer Exposure to end-to-end content creation and publishing workflows . Opportunity to work on culturally significant projects with a fast-growing team. Mentorship from senior content writers and category leaders. Possibility of a full-time role post-internship , based on performance. Apply for this position Autofill application Save time by importing your resume in one of the following formats: .pdf or .docx.

The Manager, DFT will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. You will also be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. The ideal candidate for this role should be an ASIC Design DFT engineer with 10+ years of related work experience encompassing a broad mix of technologies. You should have knowledge of the latest state-of-the-art trends in Memory testing and silicon engineering. Hands-on experience in JTAG & IJTAG protocols, MBIST, and scan architectures is essential. Your verification skills should include System Verilog, LEC, and validating test timing of the design. Experience working with gate-level simulations, and debug with VCS and other simulators is required. Understanding the testbench in System Verilog, UVM/VMM is considered an addon. Post-silicon validation and debug experience, along with the ability to work with ATE patterns, is a crucial aspect of this role. Additionally, you should possess strong verbal communication skills and the ability to thrive in a dynamic environment. Proficiency in scripting skills such as Python/Perl is also required for this position.,

You are a highly experienced RTL Design Lead responsible for driving the architecture, micro-architecture, and RTL development of digital IP/SoC blocks. Your role involves leading RTL design activities for complex IPs or SoC sub-systems and collaborating with various teams to ensure successful integration and tapeout. You will be required to mentor junior designers, support silicon bring-up, and debug as needed. To excel in this role, you must have a proven track record of delivering IP or SoC designs from spec to GDSII. Your expertise should include micro-architecture development, pipelining, clock-domain crossing, and a good understanding of the ASIC design flow. Hands-on experience with AMBA protocols and standard interfaces is essential, along with strong debugging and problem-solving skills. Familiarity with low-power design techniques is considered a plus. Preferred skills for this role include exposure to high-speed protocols, proficiency in scripting languages for automating design tasks, and experience with tools like Synopsys DC, Spyglass, Verdi, VCS, etc. Prior experience in leading and mentoring a small team is also beneficial. As an ideal candidate, you should possess a Bachelor's or Master's degree in Electronics/Electrical Engineering or a related field. Your role will involve working closely with architects to translate high-level specifications into micro-architecture and RTL, driving design reviews, coding standards, and technical quality, and defining/implementing RTL design methodologies and flows. If you are seeking a challenging opportunity to lead RTL design activities, collaborate with cross-functional teams, and contribute to the successful development of cutting-edge IPs and SoCs, this role is tailored for you.,

As an Engineer (DFT) at eInfochips located in Bangalore, India, you will be responsible for hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in the usage of Synopsys tools such as DFT MAX and TetraMAX, as well as Cadence tools like RTL Compiler, Encounter Test, modus, and Janus. Additionally, experience with Mentor Graphics tools like Tessent tool chain, TestKompress, Debussy, VCS/Questa/IUS, and PT tool from Synopsys will be advantageous. This is a full-time position falling under the category of Engineering Services.,

Wipro Limited is a leading technology services and consulting company dedicated to developing innovative solutions that cater to the most intricate digital transformation needs of clients. With a vast portfolio of capabilities in consulting, design, engineering, and operations, Wipro assists clients in achieving their most ambitious goals and establishing future-ready, sustainable businesses. The company, with over 230,000 employees and business partners operating in 65 countries, is committed to aiding customers, colleagues, and communities in thriving amidst a constantly changing world. For more information, visit www.wipro.com. As a Lead Design Verification Engineer with at least 7 years of hands-on DV experience in SystemVerilog/UVM, you will be responsible for owning and driving the verification of a block/subsystem or a SOC. An ideal candidate should have a proven track record of leading a team of engineers and possess extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Proficiency in Tesplan and Testbench development, execution of test plans using high-quality constrained random UVM tests to achieve coverage goals on time, and adeptness in debugging and exposure to all aspects of verification flow including Gatesims are essential. The candidate must have extensive experience in the verification of technologies such as PCI Express or UCIe, CXL or NVMe, AXI, ACE or CHI, Ethernet, RoCE or RDMA, DDR or LPDDR or HBM, ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages, and Power Aware Simulations using UPF. Experience in using EDA tools like VCS, Verdi, Cadence Xcelium, Simvision, Jasper, and revision control systems such as Git, Perforce, Clearcase is required. Experience in SVA and formal verification is desirable, and knowledge of script development using Python, Perl, or TCL is an added advantage. The position is available in various locations including Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, and Pune. The ideal candidate must have a minimum of 7 years of YoE. Key Responsibilities: - Define product requirements and implement VLSI and hardware devices - Continuously upgrade and update design tools and frameworks - Analyze and select the right components and hardware elements for product engineering - Conduct cost-benefit analysis to choose the best design - Develop architectural designs for new and existing products - Implement derived solutions and troubleshoot critical problems - Evangelize architecture to project and customer teams to achieve the final solution - Monitor product solution and make continuous improvements - Understand market-driven business needs and technology trends to define architecture requirements and strategy - Develop Proof of Concepts (POCs) to demonstrate product feasibility - Provide solutioning for RFPs from clients and ensure overall product design assurance - Collaborate with sales, development, and consulting teams to reconcile solutions to architecture - Provide technical leadership in designing custom solutions using modern technology - Validate solutions from technology, cost structure, and customer differentiation perspectives - Identify and resolve problem areas in architectural design and solutions - Monitor industry and application trends and provide strategic input during product deployment - Support delivery team in product deployment and issue resolution - Develop product validation and performance testing plan in alignment with business requirements - Maintain product roadmap and provide inputs for product upgrades based on market needs - Build competencies and branding through necessary trainings, certifications, and Thought leadership content development - Mentor developers, designers, and junior architects for career enhancement - Contribute to the architecture practice by conducting selection interviews Performance Parameters: - Product design, engineering, and implementation: Measure based on CSAT, quality of design/architecture, FTR, delivery as per cost, quality, and timeline, POC review and standards - Capability development: Measure based on % of trainings and certifications completed, mentorship of technical teams, and development of Thought leadership content Wipro is dedicated to reinventing your world by building a modern, end-to-end digital transformation partner with ambitious goals. The company is looking for individuals who are inspired by reinvention and are committed to constant evolution in their careers and skills. Join Wipro to realize your ambitions and be part of a purpose-driven business that empowers you to design your own reinvention. Applications from people with disabilities are explicitly welcome.,

Expertise in ASIC Verification of MAC protocols Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim , Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath , DSP based ASICs Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory Good knowledge in gate-level simulation, and Scripting languages like Expertise in Python, TCL scripting

The heart, soul, and memes of the FairDAO community. If you ve ever wanted to orchestrate chaos, curate culture and build a movement, this is it. Your Day-to-Day Role (it changes fast here) Set the Vibe Drive the Tribe Architect community growth loops: quests, pledges, seasonal vibes, collabs Define rituals: alpha drops, meme contests, game nights, Twitter raids, on-chain flexes Keep the energy high during launches, quiet moments, and everything in between Run the Playground, Not Just the School Lead Discord, Telegram and Twitter fam: keep spam out, fun in Own reward systems: leaderboards, contributor roles, quest XP, FairDAO token perks Turn feedback loops into product, token, and growth insights Lead the Mods, Inspire the Squad Build and mentor a mod army: no passive lurkers Write playbooks so clean other DAOs steal them Set KPIs that actually matter (sentiment > follower counts) Be the Bridge Sync with Product, Marketing & Growth on launches, token events, ecosystem plays Translate deep tech into human-speak and meme-speak Amplify member voices into roadmap ideas & brand moments You ll Thrive Here If You: Have hands-on experience managing pre and post token launch journeys (big launch energy is a must) Have built and grown Web3 (or gaming, fandom, creator) communities from 0 thriving Can vibe with degens, explain stuff to normies and battle trolls with grace Think in memes, rituals, and flywheels, not just Discord channels Know tokenomics & community incentives IRL, not just on paper Love data but trust your gut when needed Care about giving contributors ownership, not just engagement bounties Bonus XP: Survived a bear market with your sense of humor intact Why You ll Love This Lead the narrative & vibe of a fast-growing Web3 infra protocol Work with founders who actually listen to community Ship fast, break norms, build public goods Competitive comp + tokens (yeah, we said it)

Responsibilities: *Strong knowledge of DDR protocols (DDR3/DDR4/LPDDR4/LPDDR5). *Proficiency in gate-level simulations and debugging. * Familiarity with JTAG-based testing and silicon validation flows. Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

Role & Responsibilities At DrinkPrime, we have a vision of disrupting the water industry. We believe that technology has a key role to play by providing a highly scalable platform that can seamlessly connect and control millions of devices. We are looking for people who are technically excellent and, at the same time, enjoy the excitement and unpredictability of working in a startup environment. You will be working closely with the senior leadership and have a great opportunity to be part of the core technology team. We are a well-funded high-growth startup currently operating in Bangalore and have a great open environment. Were currently in hybrid mode and would prefer our employees to be located in Bangalore after joining. As a junior developer, your role would be to: Develop responsive frontend for the web and internal dashboards Interface with the backend team to test and integrate requisite APIs Build test plans and implement a rigorous testing process Work with the design team to understand and optimize user journeys Be involved in strategic decisions involving UX and the technology stack Our ideal candidate would be someone who has 6m+ of relevant experience as an intern or in a full time role. Hands-on knowledge of JS & JS frameworks like React JS, Vue JS, etc. Experience in CSS/SASS and prototyping tools is a plus.

Job Roles: * Design DFT solutions using architecture, JTAG,VCS tools. * Strong knowledge of DDR protocols (DDR3/DDR4/LPDDR4/LPDDR5). * Proficiency in gate-level simulations Mail: chaitanya.vasamsetti@gigaopsglobal.com Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

At QpiAI, we are leading the effort to discover optimal AI and Quantum systems in Life sciences, Healthcare, Transportation, Finance, Industrial, and Space technologies. QpiAI is building a full stack Enterprise Quantum Computers. QpiAI Quantum hardware team is responsible for designing and characterization of Quantum Processor, Cryogenic Quantum Control Circuits, RF Control Hardware, and QpiAI ASGP. We are seeking a skilled and motivated Hardware Verification Engineer to join our Hardware team. Together, we will build the next generation of life changing custom hardware for Quantum computers! If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be. In this position, you will be creating models and test plans for verifying functionality and performance of inhouse chip designs. You will understand the design, define the verification scope, develop the verification infrastructure, and verify the correctness of the design. Requirements: - BS or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science or related degree required, advanced degrees (MS, PhD) preferred - 3+ years of relevant work experience - Proficiency in verification languages (System Verilog or equivalent) and methodologies (UVM or equivalent) - Experience with verification tools such as VCS and Verdi - Good debugging and problem-solving skills Join us at QpiAI and be part of a team that is shaping the future of Quantum computing hardware!,

Join us as a Full-Stack Software Engineer at Barclays, where you will play a crucial role in driving innovation and excellence in our digital landscape. Your primary responsibility will be to leverage cutting-edge technology to enhance our digital offerings, ensuring exceptional customer experiences. Working alongside a team of developers, you will be tasked with delivering technology solutions, utilizing your strong analytical and problem-solving skills to comprehend business requirements and deliver high-quality results. To excel in this role, you should possess experience in: - Core Java (Java 11) - Spring Boot, Spring framework - Bootstrap, HTML, CSS, JavaScript, Angular - MongoDB, SQL - CI/CD Pipelines (Jenkins, GitLab) Additionally, highly valued skills include proficiency in: - APIs and Servicemesh architecture - Test frameworks such as JUnit, Mockito - Tools like Postman, Insomnia - Cloud platforms like AWS, Google Cloud - Unix bash scripting - Version Control Systems (Git) - Stakeholder Management - Requirement Analysis - Design document creation Your performance may be evaluated based on critical skills crucial for success in this role, including risk and controls, change and transformation, business acumen, strategic thinking, and digital and technology expertise. This position is based in Pune. **Purpose of the Role:** Your main objective will be to design, develop, and enhance software using various engineering methodologies to provide business, platform, and technology capabilities for our customers and colleagues. **Accountabilities:** - Develop and deliver high-quality software solutions using industry-aligned programming languages, frameworks, and tools, ensuring scalability, maintainability, and performance optimization of the code. - Collaborate cross-functionally with product managers, designers, and engineers to define software requirements, devise solution strategies, and integrate seamlessly with business objectives. - Participate in code reviews, promote a culture of code quality and knowledge sharing, and stay updated on industry technology trends. - Adhere to secure coding practices, implement effective unit testing, and ensure proper code design, readability, and reliability. **Analyst Expectations:** - Perform activities in a timely manner with high standards, driving continuous improvement. - Demonstrate in-depth technical knowledge and experience in your area of expertise. - Lead and supervise a team, guide professional development, allocate work, and coordinate resources effectively. - If in a leadership role, exhibit leadership behaviors to create an environment for colleagues to excel. For individual contributors, develop technical expertise, acting as an advisor when needed. - Partner with other functions and business areas, take ownership of team activities, and escalate policy breaches appropriately. - Advise decision-making, manage risk, strengthen controls, and adhere to relevant rules and regulations. - Understand how your sub-function integrates with the broader function, organization's products, services, and processes, and contribute to achieving organizational objectives. - Resolve problems, guide team members, communicate complex information, and build a network of contacts. All colleagues are expected to embody the Barclays Values of Respect, Integrity, Service, Excellence, and Stewardship, as well as demonstrate the Barclays Mindset to Empower, Challenge, and Drive.,

In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. You have the opportunity to join the Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, two industry leaders have united to create an optical networking powerhouse, combining cutting-edge technology with proven leadership to redefine the future of connectivity. As an FPGA Verification engineer, you will play a crucial role in designing verification plans, developing environment/testbenches, creating test scenarios for running simulations, conducting coverage analysis, and providing lab support during board bring up to ensure the quality of Infinera products. You should possess the ability to handle projects independently and demonstrate a strong drive for finding solutions. Your responsibilities will include developing and executing verification plans for high-complexity DWDM systems used in LH/ULH optical network applications, designing and implementing simulation environments and testbenches, running test scenarios to ensure comprehensive design coverage, performing coverage analysis, collaborating with cross-functional R&D teams, providing lab support during board bring-up, and managing verification projects independently with a proactive approach. Key skills and experience required for this role include 12-16 years of experience in developing System Verilog UVM based test environments, HVL coding skills for Verification, familiarity with UVM verification methodologies, knowledge of HDLs such as Verilog and scripting languages like perl, conversance with technologies like Ethernet, PCIe, I2C, SPI, structured analytical and troubleshooting skills, good communication skills, and a self-driven and innovative mindset. Nokia is committed to innovation and technology leadership across mobile, fixed, and cloud networks. Joining Nokia will provide continuous learning opportunities, well-being programs, opportunities to join employee resource groups, mentoring programs, and the chance to work in highly diverse teams with an inclusive culture. Nokia is an equal opportunity employer committed to creating a culture of inclusion where everyone feels respected, included, and empowered to succeed.,

As an experienced Verification Engineer with a minimum of 5 years of experience, your primary responsibility will be to lead the verification of DDR memory controller and PHY designs in compliance with DDR standards like DDR3, DDR4, DDR5, and other memory interface protocols. You will be required to develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM, and other industry-standard methodologies. Ensuring protocol compliance is crucial, which includes validating command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Your role will involve creating detailed verification plans based on DDR specifications and requirements, focusing on corner cases, timing, and protocol validation for full coverage. Running simulations, debugging issues using tools like Questa, VCS, or ModelSim, and applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage will be part of your daily tasks. You will set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues. Achieving high functional and protocol coverage is vital, ensuring that timing constraints, corner cases, and failure scenarios are thoroughly verified. Implementing formal verification techniques to validate critical components of the DDR design, ensuring correctness in timing and data flow, and verifying crucial operations will also be part of your responsibilities. This position requires a Bachelor's or Master's degree in ECE/EEE or VLSI/Electronics from a reputable institution. The position is based in Bangalore/Hyderabad.,

You will be a lawyer for a Partner-Funds position at a reputable full-service law firm located in Mumbai. As a senior legal professional, you are expected to have demonstrated expertise in fund formation, structuring, and regulatory advisory. Your role will involve leveraging a strong client network and being capable of leading mandates independently. Experience in managing Alternative Investment Funds (AIFs), Venture Capitalists (VCs), Private Equity (PE) funds, and related transactions is essential. Holding a full-time LLB degree is mandatory for this position. Preference will be given to candidates who have a team and are interested in transitioning together.,

As a Senior/Lead/Sr. Lead Design Verification Engineer at our company located in Bangalore or Hyderabad, you will play a crucial role in ensuring the verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need to have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 4 years of hands-on experience in this domain. Your responsibilities will include utilizing your expertise in SystemVerilog and UVM to develop verification components like scoreboards, monitors, and sequencers. You will be required to have a strong understanding of digital design principles, verification methodologies, and simulation tools. Additionally, familiarity with protocol specifications and industry standards for DDR, PCIe, UCIe, or NVMe will be crucial for this role. Having experience with simulation tools such as VCS, ModelSim, or Questa will be an added advantage. You should also possess good debugging skills using tools like Waveform Viewers, Logic Analyzers, and protocol analyzers. Problem-solving skills, attention to detail, and the ability to work collaboratively are essential traits for this position. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, and proficiency in scripting languages like Python for automation purposes. Familiarity with FPGA-based verification platforms and hardware debugging tools will be beneficial in excelling in this role. If you are looking to join a dynamic team where you can leverage your skills in design verification and work on cutting-edge technologies, this position is ideal for you. Join us in our mission to push the boundaries of innovation and make a significant impact in the field of high-speed interface verification.,

As a Solaris Administrator, you will be responsible for the installation, implementation, customization, operation, recovery, and performance tuning of Solaris Operating Systems. Your role will involve installing and maintaining all Solaris server hardware and software systems, administering server performance and utilization, and ensuring availability. Additionally, you will be required to prepare program-level and user-level documentation as needed. Your key responsibilities will include supporting infrastructure implementations, deployments, and technologies related to dynamic infrastructure platforms. You will participate in current state system analysis, requirements gathering, and documentation. Moreover, you will contribute to the creation of technical design/implementation documentation and assist in requirements understanding and issue resolution. Furthermore, you will be involved in tasks such as maintaining and installing Oracle ZFS Storage, troubleshooting and maintaining Solaris Operating Systems (8, 9, 10, and 11), patching Solaris systems with Sun cluster and VCS, configuring APACHE web server on Solaris and Linux, creating and extending Volume Groups and file systems, resolving sudo issues, working with VERITAS volume manager and cluster, managing users and groups in NIS and LDAP servers, and installing, upgrading, and patching Solaris servers. You will also handle Solaris server decommissioning, VERITAS cluster monitoring, starting and stopping cluster services, moving resource groups across nodes, increasing file systems in cluster file systems, synchronizing cluster resources, and creating and deleting new cluster service groups and resources. Your expertise should include Solaris server performance monitoring, kernel tuning, and troubleshooting. Additionally, you should have experience working with ticketing tools like Remedy and ManageNow, knowledge of OS clustering, partitioning, virtualization, and storage administration, integration with operating systems, and the ability to troubleshoot capacity and availability issues. You will collaborate with project teams to prepare components for production, provide support for ongoing platform infrastructure availability, and work on prioritized features for ongoing sprints. In this role, you will be accountable for completing the work you lead and deliver quality work to the team. The position falls under the IT Support category with a salary as per market standards. The industry focus is on IT Services & Consulting within the functional area of IT & Information Security. This is a full-time contractual employment opportunity.,

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test-bench issues and failures. As part of this role, you will be accountable for verification closure by focusing on coverage and managing bug reports. Proficiency in utilizing industry-standard verification tools like Questa, VCS, or ModelSim is required. Experience with scripting languages like python, perl, or TCL for automation tasks is also beneficial. Furthermore, you will be responsible for managing a team of 6 to 7 Engineers and engaging with customers to provide task updates. Experience in collaborating with Japanese customers is a prerequisite for this position. Proficiency in the Japanese language is a mandatory skill. If you meet these qualifications and are enthusiastic about taking on these responsibilities, we encourage you to apply for this challenging and rewarding role.,

Are you interested in a unique opportunity to be a part of something great Would you like to join a 20,000-member team that is at the forefront of technology that powers the world around us Microchip Technology, Inc. offers an environment of trust, empowerment, respect, diversity, and communication. You will have the chance to own a piece of a multi-billion dollar global organization and more. At Microchip, employees are part of a culture that supports growth and stability. They are engaged and motivated by a wide range of products and solutions with unlimited career potential. The nationally-recognized Leadership Passage Programs at Microchip facilitate career growth for over a thousand individuals annually. The company is committed to employee development, values-based decision making, and fostering a strong sense of community based on its Vision, Mission, and 11 Guiding Values. This commitment has earned Microchip numerous awards for diversity and workplace excellence. As a Verification Engineer at Microchip, your responsibilities will include playing a key role in block-level verification. You will develop verification test plans based on design specifications, create test environments using System Verilog and UVM methodologies, and integrate with RTL while conducting basic simulation bring-up for the design. You will be tasked with generating code/functional coverage, analyzing coverage results, correlating them with the test plan, creating multiple test cases, and launching regressions. Additionally, you will collaborate with the design team to quickly identify and resolve design issues. The ideal candidate for this role will have expertise in domains such as AHB, AXI, PCIe, USB, and Ethernet. Proficiency in Verilog and System Verilog is essential, as well as familiarity with at least one of the following methodologies: OVM, UVM, VMM. Experience with EDA tools like Questasim, VCS, NCSim, or NCVerilog is required. You should have experience in developing test bench components at both block and SOC levels, creating test plans, and writing test sequences. Knowledge of functional coverage, code coverage, and assertions (OVA, SVA, PSL) is desirable. Strong analytical, problem-solving skills, excellent written and verbal communication in English, and a passion for teamwork and excelling in a competitive environment are also essential. Qualifications for this role include a Bachelor's Level Degree (ECE, EE / preferred specialization) with more than 9 years of work experience. The role may involve up to 25% travel time. Please note that Microchip Technology Inc. does not accept unsolicited agency resumes. Kindly refrain from forwarding resumes to the recruiting team or other Microchip employees, as the company is not responsible for any fees related to unsolicited resumes. Visit our careers page to explore exciting opportunities and company perks.,

We are seeking an experienced RTL Design Engineer to be a part of our advanced ASIC/SoC development team in Bengaluru. As an RTL Design Engineer, you will be responsible for developing high-quality, synthesizable RTL code using Verilog/SystemVerilog and integrating complex IPs and subsystems into high-performance SoCs. Collaboration with system architects, contribution to micro-architecture, and ensuring design quality through checks like Lint, CDC, and Synthesis will be key aspects of this role. Your responsibilities will include leading SoC-level integration activities, providing technical guidance in design reviews, and interfacing with cross-functional teams for smooth bring-up and signoff processes. The ideal candidate should possess a Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, along with at least 7 years of experience in RTL design and SoC integration. Strong skills in Verilog/SystemVerilog, knowledge of SoC architecture and bus protocols, and proficiency in industry tools like Design Compiler, Spyglass, and VCS are essential for this role. If you have a deep understanding of clock/reset strategies, hierarchical design practices, timing closure, synthesis flows, and constraints development, along with strong analytical and debugging skills to resolve complex RTL and integration issues, we would like to hear from you. Join us and contribute to the design, integration, and verification of cutting-edge IPs and subsystems within high-performance SoCs.,

About InstaNode & Helium Wars At the forefront of Web3 infrastructure and gaming innovation, InstaNode is redefining how decentralized applications access and optimize blockchain nodes, while Helium Wars is a next-generation Web3 gaming platform that fuses immersive gameplay with on-chain utility and digital assets. We are seeking a Co-Founder Fundraising & Strategy with a proven track record in leading high-impact B2B/B2C products across Web3 Gaming, Fintech, Infra, or DeFi verticals. This is a rare opportunity to join as a strategic co-builder, lead capital-raising efforts, and shape the product vision alongside experienced founders. Key Responsibilities Product Leadership & Strategy Drive the product roadmap in collaboration with tech, marketing, and design teams Scale the offering and sales of the products Build an ecosystem partnership to increase the business and revenue numbers Overall responsible for driving the business and growing the product Fundraising & Investor Engagement Lead fundraising efforts across pre-seed, seed, and growth rounds. Build and manage relationships with crypto-native VCs, angels, DAOs, and family offices. Own investor communication, pitch deck creation, and due diligence processes. Tokenomics & Financial Modeling Co-create scalable, incentive-aligned tokenomics models for Helium Wars and infrastructure usage for InstaNode. Collaborate with legal, compliance, and launch partners on token sales (if applicable). Develop financial forecasts, revenue models, and valuation strategies. Ecosystem Growth & Partnerships Forge strategic partnerships with Web3 ecosystems, L1s/L2s, guilds, launchpads, and infrastructure platforms. Represent both ventures in global blockchain events, summits, and community initiatives. Key Skills & Experience Must-Have: Prior experience as a founder, Product Leader, or senior leader in scaling B2B/B2C/Web3 Gaming/Infra/DeFi/Fintech products. Deep understanding of Web3 funding models , crypto-native fundraising , and investor ecosystems. Hands-on experience working with tokenized economies or on-chain monetization strategies. Strategic thinker with operational excellence and a get-it-done mindset. Strong storytelling and pitch skills for engaging investors and partners. Good to Have: Existing relationships with Web3 VCs , angel investors, DAOs, and ecosystem players. Experience in Web3 economy design , NFTs, Infra, or play-to-earn models. Knowledge of DeFi protocols, liquidity strategies, and token launch best practices. Comfort navigating both early-stage chaos and growth-stage scale-up operations. Why Join as a Co-Founder? Shape the future of decentralized gaming and infra from Day 0. Be part of a bold, builder-driven founding team creating global-scale products. Significant equity ownership and leadership in two high-potential Web3 verticals. Lead fundraising and investor strategy with creative freedom and full-stack support.