The job is located in Bangalore and requires 3-5 years of experience for 2 available positions. The primary responsibility involves RTL Design, with a focus on practical experience in RTL development using VHDL and/or Verilog. This includes functional and structural RTL design, design partitioning, simulation, regression, and collaboration with design verification teams. The ideal candidate should be familiar with the latest RTL languages and tools such as Modelsim, VCS, Design Compile, Prime Time, Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, among others. Desirable experience includes strong processor architecture knowledge, microarchitecture implementation, microprocessor integration, and low power design. Effective communication skills, teamwork abilities, self-direction, and time management skills are essential for this role. Preferred qualifications include developing RTL for multiple logic blocks of a DSP core, running various frontend tools for linting, clock domain crossing, and synthesis, collaborating with the physical design team on design constraints and timing closure, working with the power team on power optimization, and collaborating with the verification team on test plan, coverage plan, and coverage closure. The educational requirement for this position is a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field.,
As an experienced ASIC/SoC designer with 3-5 years of experience, you will be responsible for the following key responsibilities: - Definition and development of signoff methodology and corresponding implementation solution. - Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. - Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC. - Streamlining the timing signoff criterions, timing analysis methodologies and flows. - Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow. - Collaborate with Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address the design challenges in the context of the block, chip, and overall system. - Implement concepts of CRPR, clock paths analysis and tweaks to meet timing. - Perform Multi Corner and MultiMode analysis. - Ensure close timing at SignOff corners covering the entire modes, delay corners for cells and interconnects. Qualifications Required: - 3-5 years of experience in ASIC/SoC design & implementation. - Specific background in the areas of synthesis, SignOff STA. - Experience with lower technology nodes like 40nm and below till 14nm/10nm. (Note: No additional details of the company were present in the provided job description.),