Posted:1 day ago|
Platform:
Work from Office
Full Time
We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug.
Key Responsibilities:Define and implement DFT architecture for digital and mixed-signal SoCsPerform scan insertion, boundary scan, and ATPG pattern generationIntegrate Memory BIST (MBIST) and Logic BIST (LBIST)Drive DFT verification and post-silicon validation/debugCollaborate with RTL, synthesis, STA, and backend teams to ensure testabilityEnsure high test coverage, test time optimization, and compliance with ATE requirements
Requirements:8+ years of experience in DFT implementation and verificationHands-on experience with tools like Tetramax, TestMax, Fastscan, or MBISTArchitectStrong understanding of scan/ATPG, JTAG, BIST, and IEEE 1149.x standardsExperience in silicon bring-up, failure analysis, and debugFamiliarity with industry-standard flows and ATE constraintsExcellent problem-solving and team collaboration skills
How to Apply:If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of DFT.
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