253 Vlsi Design Jobs

As a SoC Power Management Design Engineer at AMD, your role will involve developing and designing custom silicon for gaming consoles, datacenter, client, or embedded computer vision SOCs and related platforms. You will collaborate with the lead SoC architect to define customer-specific architectures, contribute to product specifications, and make performance and power trade-offs. Your work will span from early concept development through final production, requiring excellent organization and communication skills. You will work with expert architects and designers globally, presenting your findings to colleagues and customer engineering teams. Key Responsibilities: - Drive physical design and power architecture based on customer-specific requirements - Collaborate with AMD's Engineering teams and IP teams to aid in integration, implementation, and optimization of designs - Analyze power consumption and delivery using static, dynamic models, and emulation data - Evaluate performance across voltages for DVFS states of IPs, including inference engines, CPUs, Graphics, memory controllers, peripheral interfaces, caches, and network-on-chip fabric - Establish voltage-frequency design points in collaboration with technology teams, silicon validation, and product engineering teams - Define definitions for on-die PDN, power gating, package, and system power delivery in coordination with systems and architecture team - Analyze effects of control algorithms for management throttling mechanisms to optimize performance within thermal and peak current limits Preferred Experience: - Solid understanding of SoC construction, including fabric connectivity, memory systems, power delivery, clock distribution, floor planning, and packaging - Strong knowledge of SoC power management, power dissipation, and mobile battery life - Proficiency in scripting, data analysis, EDA tools, physical design tools for power optimization, VLSI design flow, and CMOS technology - Ability to model thermal control loops and throttling mechanisms - Strong problem-solving, organizational, and communication skills with the ability to work in a dynamic and diverse environment - Proficiency in scripting languages, particularly Python, is highly preferred - Experience with Power Architect, Power Artist, and VisualSim is a plus - Detail-oriented thinking skills and ability to tackle novel problems from different perspectives and levels of abstraction - Capability to analyze and streamline sophisticated workflows and processes through innovative automation Academic Credentials: - Bachelors or Masters degree in computer engineering/Electrical Engineering (Note: The benefits offered are described separately in the AMD benefits overview.),

The Core design and verification team is responsible for development of High performance and Ultralow power x86 microprocessor core . The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. THE PERSON: Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. KEY RESPONSIBILITIES: ASIC design verification experience 6 to 10 years. Verification of high performance x86-core ISA features Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor. Development of detailed test plans and driving the execution of test plan, including functional coverage. Understanding the existing test bench setup and look for opportunities to improve the existing test bench. Adhering to coding guideline practices, develop and implement code review process. Collaborate with global design verification teams and drive effectively the execution of the verification plans. Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: Strong understanding the design and verification life cycle. Hands on verification experience with C/C++/SystemVerilog testbench development. Hands on experience with coverage planning, coding and coverage closure. Experience with x86, ARM or any other industry standard microprocessor ISA. Experience with Cache, Coherency and Data-Consistency verification. Experience in clocking, reset, power-up sequences and power management verification. Knowledge of microprocessor design-for-debug (DFD) logic will be a plus. Understanding of low power design verification techniques is a plus. ACADEMIC CREDENTIALS: Master s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

NIET is looking for highly motivated and qualified individual to join our faculty as an Assistant Professor/Associate Professor in ECE (VLSI). The successful candidate will be expected to contribute to the teaching, research, and other administrative activities of the department. Responsibilities: Teach courses in VLSI design, digital electronics, and related areas. Develop and maintain a strong research program in VLSI design, leading to publications in peer-reviewed journals and presentations at international conferences. Supervise graduate and post graduate student research projects. Participate in curriculum development and assessment. Seek and obtain external funding for research projects. Collaborate with other faculty members on interdisciplinary research projects. Stay current with the latest developments in VLSI technology and incorporate them into teaching and research. Qualifications: M. Tech.- VLSI is mandatory qualification. Candidates having Ph.D. in Electrical Engineering or a closely related field will be given advantage. Preference will be given to candidates who have completed a VLSI course from CDAC. Strong background in VLSI design, digital electronics, and related areas. Excellent communication and interpersonal skills. Ability to work effectively in a team environment.

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. Job Description In your new role you will: The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the vectors, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Your Profile You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 8+ years of in DFT implementation, verification and post silicon debug areas

Job Requirements PD Trainee Engineer Role Summary: We are looking for enthusiastic entry-level engineers to join our VLSI Physical Design (PD) team. As a trainee, you will learn and contribute to various stages of the chip design flow under the guidance of Lead engineers. Key Responsibilities: Assist in physical design activities such as floor planning, placement, clock tree synthesis, routing, and timing closure. Work with senior engineers to run EDA tools for design implementation and verification. Support design checks for power, performance, and area (PPA). Learn industry-standard flows for DRC, LVS, and STA. Document processes and contribute to knowledge sharing within the team. Work Experience Requirements: B.E/B.Tech/M.Tech in Electronics Basic understanding of digital circuits and CMOS. Good analytical and problem-solving skills. Eagerness to learn VLSI PD flows and EDA tools. Strong teamwork and communication skills. Exposure to VLSI design flows through coursework, projects, or internships. Knowledge of scripting (TCL, Perl, Python, or Shell).

Job Requirements We are seeking a highly motivated Trainee Engineer to join our esteemed VLSI Design for Test (DFT) team. The selected candidate will actively participate in design-for-test methodology, with a specific focus on MBIST and scripting for automation. Key Responsibilities: Provide support to the DFT team in the implementation and verification of test structures. Engage in MBIST (Memory Built-In Self Test) design, integration, and validation. Create and maintain automation scripts (TCL/Perl/Python) for design and test flows. Assist in the identification and resolution of DFT-related issues. Collaborate closely with design and verification teams to ensure the delivery of high-quality results. Required Skills: Foundational understanding of DFT concepts (Scan, MBIST). Hands-on experience in MBIST implementation. Proficiency in scripting languages such as TCL, Perl, Python, and Shell. Demonstrated problem-solving and debugging abilities. A strong desire to learn and contribute within a team-oriented environment. Qualification: B.E/B.Tech or M.E/M.Tech in Electronics Work Experience Required Skills: Basic understanding of DFT concepts (Scan, MBIST). Hands-on experience in MBIST implementation. Scripting skills in TCL/Perl/Python/Shell. Good problem-solving and debugging skills. Strong willingness to learn and work in a team environment.

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Mandatory Skills: VLSI Design For Testability - DFT . Experience: 8-10 Years .

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route . Experience: 3-5 Years .

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Analog Layout . Experience: 3-5 Years .

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Semiconductor Integration . Experience: 3-5 Years . >

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 4+ years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Overview: This position centers onfloor-planning expertise at both block and top levelsfor industry-leadingCPU core designs, with a strong emphasis on scalability and achieving aggressivePower, Performance, and Area (PPA)targets. The role involves working oncutting-edge technology nodesand applyingadvanced physical design techniquesto push the boundaries of CPU performance and efficiency. Preferred Qualifications: Masters degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience In depth end to end experience from RTL2GDS, taping out at least 5 complex designs Direct hands-on experience with bus/pin/repeater planning for entire IP Key responsibilities include: Drivingfloorplan architecture and optimizationin collaboration with PD/RTL teams to maximize PPA Engaging incross-functional collaborationwith Physical design, timing, power, and packaging teams to ensure holistic design convergence Partnering withEDA tool vendorsand internal CAD teams to develop and enhanceautomation flows and methodologiesfor improved design efficiency Makingstrategic trade-offsin design decisions to achieve optimal PPA outcomes while maintaining schedule and quality targets End to End Physical verification closure for subsystem. The ideal candidate will have/demonstrate the following: Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, big and high speed designs Experience with physical synthesis and implementation tools - Cadence Innovus/Genus and Synopsys Fusion Compiler. Must have good knowledge of static timing analysis, reliability, and power analysis Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks Strong understanding of CPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance Solid working knowledge of scripting skills including tcl, perl or python Excellent communication skills and collaborating in a team environment is a must Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues. (Mostly Working on Calibre tool) Experience in IO, Bump planning and RDL routing Strategy. Preferred Skills: Clock implementation, power delivery network design choices, process technology, prior experience in flow and methodology development, block closure Close interaction with design and architecture teams to influence scalable floor-plans and optimal bus/pin/repeater planning for entire IP and its sub-blocks Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff Hands on experience working with very complex designs that push the envelope of Power, Performance and Area Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous Hands on experience on Innovus/FC tool based scripting & python/TCL scripting. Prior experience in flow and methodology development is an advantage Excellent debug and analytical skills and demonstrated successes in floor-planning large IP and high frequency designs Ability to drive Physical Implementation teams in Floor-planning and work well in a collaborative environment with multi-disciplined teams Minimum Qualifications: Bachelors degree in Electrical/Computer Engineering 8+ years of direct top level floor-planning large and high frequency IP experience which includes bus/pin/repeater planning at the top level Strong background in VLSI design, physical implementation and scripting Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools Hands on experience taping out designs in sub-micron technology node design less than 10nm Expect strong self-motivation and time management skills

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 4+ years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, And should be familliar to PNR tools like Innovus/FC Solid grip on STA fixing aspects to solve extreme critical timing and clock path analysis Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs and manual ECOs as well. Experience in deep submicron process technology nodes is strongly preferred - Below 10nm Knowledge of high performance and low power interface timing is added benefit. Strong fundamentals on basic VLSI design concepts, synchronous design timing checks, understanding of constraints Good experience with in Unix, TCL, PT-TCL, Tempus-TCL scripting Familiarity with Python background is added bonus.

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

DFT Engineers with experience in ATPG, MBIST, post-silicon debug. Tools: TestKompress, VCS RTL Engineers with Verilog, SoC/IP design, PCIe/DDR, Spyglass. Tools: DC, Verdi, Xcelium. Physical Design Engineers with experience in Innovus, STA, 28nm Office cab/shuttle Food allowance Health insurance

This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top. Candidate will work on various stages of physical design implementation which includes floorplanning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IRdrop, physical verification checks. Candidate is expected to have deep understanding and hands-on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques. Candidate should have good understanding of IO planning, package co-design aspects. Candidate is expected to drive flow/methodology activities to improve upon QoR. You are best equipped for this task if you have: Bachelors or Masters degree with specialization in VLSI design. Hands-on experience in physical design and timing closure of SoCs. Experience of industry standard tools for physical design and signoff. Experience in scripting languages (shell, perl, tcl) and Make flow. Understanding of 40nm/28nm technologies and associated physical design challenges. Must be a good team player and should have desire to learn and explore.

STA and Timing closure of Infineon SoCs targeted for IoT and MCU markets. Job Description Responsible for leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond). Ownership of constraints development for functional/test modes at pre and post layout stage. Opportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces. Timing analysis and convergence of large hierarchical design across multiple modes and corners. Interact with RTL and DFT teams on timing feasibility and performance assessment. Work closely with physical design team for timing/SI closure Your Profile B.Tech or M.Tech relevant work experience and specialization in VLSI design. Strong hands-on technical experience in constraints development, timing analysis/closure of SoCs. Experience in low-power synthesis and equivalence checks will be a plus. Expert user of industry standard tools for timing signoff. Experience in scripting languages (shell, perl, tcl) and Make flow. Must be well organized, methodical and detail oriented.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT . Experience: 3-5 Years .

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Physical Place and Route . Experience: 1-3 Years .

The role of Memory Circuit Design Engineer at Synopsys India Pvt Ltd is a full-time position suitable for individuals with 2 to 6 years of relevant experience. The position is based in Bengaluru with the flexibility of working partially from home. As a Memory Circuit Design Engineer, you will be tasked with the design, optimization, and verification of memory circuits. Collaboration with cross-functional teams is an essential aspect of this role to ensure that the memory designs adhere to industry standards. Your responsibilities will also include circuit simulation, analysis, debugging, and documentation. To excel in this role, you should possess strong skills in Memory Circuit Design, Circuit Simulation, and Analysis. Experience with Verification and Debugging techniques is crucial, along with proficiency in using CAD tools and EDA software. Excellent collaboration and communication skills are necessary for effective interaction within the team. The ability to work efficiently in a hybrid work environment is also a key requirement. Candidates for this position should hold a Bachelor's or Master's degree in Electrical Engineering or a related field. Knowledge of CMOS, VLSI design, and semiconductor device physics will be beneficial for successfully fulfilling the responsibilities associated with this role.,

The ideal candidate for this position should have an ME/MTech qualification in Signal Processing, Communication Systems, or VLSI Design. You will be responsible for developing and implementing signal processing algorithms, firmware for various interfaces in Radar. You should possess hands-on experience in working with Embedded Hardware and Firmware designs. Your responsibilities will include algorithm development, simulation, and implementation using Vivado, Matlab, or Python. You will also be involved in Radar Subsystem integration and testing, Embedded Hardware, and Firmware development using FPGA, DSP, or Microcontroller. Additionally, you will work on high-speed ADC, DAC, DDR, Ethernet, and other peripheral interface designs with FPGA. To excel in this role, you should have experience with FPGA design tools such as Vivado, Vitis HLS, System Generator, and PCB/Schematic design tools like Cadence, Allegro PCB Editor. Knowledge of various communication protocols like Ethernet, Serial, CAN, VME, VPX, etc., will be beneficial. The ideal candidate should have at least 3 years of experience in firmware design, FPGA, or DSP, with a focus on radar applications. Proficiency in programming languages such as VHDL, Verilog, and C Programming is required. Knowledge of Radar Signal Processing, Matlab, and hands-on experience with Vivado FPGA tools is essential. Experience in RF-ADC/DAC, RFSoC interfaces, Python will be considered desirable for this position.,