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ASIC DV Lead

10 - 14 years

0 Lacs

hyderabad telangana

Posted:1 day ago| Platform: Shine logo

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Skills Required

soc ip system verilog uvm ethernet pcie ddr usb debugging questa vcs modelsim python perl asic block level functional verification tcl

Work Mode

On-site

Job Type

Full Time

Job Description

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test-bench issues and failures. As part of this role, you will be accountable for verification closure by focusing on coverage and managing bug reports. Proficiency in utilizing industry-standard verification tools like Questa, VCS, or ModelSim is required. Experience with scripting languages like python, perl, or TCL for automation tasks is also beneficial. Furthermore, you will be responsible for managing a team of 6 to 7 Engineers and engaging with customers to provide task updates. Experience in collaborating with Japanese customers is a prerequisite for this position. Proficiency in the Japanese language is a mandatory skill. If you meet these qualifications and are enthusiastic about taking on these responsibilities, we encourage you to apply for this challenging and rewarding role.,

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