30 Questa Jobs

Position: Senior FPGA Engineer Company: izmo Microsystems Ltd. Location: Whitefield, Bangalore ## Only Immediate Joiners ## izmo Microsystems (www.izmomicro.com) is a leading semiconductor and systems company based in Bangalore, specializing in advanced System-in-Package (SiP), silicon photonics packaging, and high-speed interconnect solutions. Backed by deep expertise in 3D packaging and photonic integration, we also design complete embedded and FPGA-based system platforms for data centers, telecom, automotive, and intelligent devices. We combine proven capability with innovation to power next-generation electronic systems. Job Summary: We are seeking a highly skilled Senior FPGA Engineer w...

As a Senior FPGA Design Engineer with 7+ years of experience, you will be responsible for designing high-performance FPGA systems for next-generation computing and connectivity. Your key responsibilities will include: - Designing, architecting, and developing FPGA RTL (VHDL/Verilog) logic for high-speed serial protocols. - Handling CDC, multi-clock domains, SerDes, and timing closure challenges. - Performing FPGA synthesis, place & route, and timing optimization using Xilinx Vivado. - Validating FPGA and board-level issues to ensure reliable high-speed interface performance. - Collaborating with global R&D teams and leveraging AI-assisted tools to enhance development productivity. To qualify...

Role Overview: As an ASIC/SOC Front End DV (Design Verification) Engineer, you will play a crucial role in the development of TB architecture definition and TB infrastructure/test coding for PCIe/Networking/IP Sub-Systems. Your responsibilities will include understanding product specifications, developing verification plans, test plans, coverage plans, assertions, and more. You will be expected to collaborate with team members, work on verification methodologies, and contribute to process improvements. Key Responsibilities: - Develop TB architectures and verification environments based on SV/UVM methodology - Create verification plans, test plans, coverage metrics, and assertions - Implement...

You will be part of a dynamic and motivated team, collaborating with Systems, Design, DFT, Mixed Signal, and other local/remote teams to address verification challenges related to IPs, SubSystems, and overall systems. Your role will involve utilizing advanced verification languages and methodologies to achieve first pass success of complex IPs. - Evaluate and implement evolving verification methodologies for handling complex IP/SubSystem designs within tight schedules - Ensure quality adherence throughout all project stages, analyzing existing processes and implementing improvements for Zero Defect IPs/SubSystems - Contribute to technological innovations for self and team development - Work ...

Job Title: Design Verification Engineer Exp Level:4+yrs Location: Bangalore/Hyderabad Job Description: Responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration: Work with RTL designers to identify and resolve design bugs. Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug. Protocols: Verify IP/SoC-level designs for common protocols (AXI, APB, PCIe, DDR, etc.)...

The DFT Engineer will focus on developing and implementing Design for Test strategies and techniques to test the complex IoT products which has WIFI & Blue tooth combo devices. He will work closely with design and backend, verification teams to ensure robust testing mechanisms and improve overall product quality and reliability. Job Description In your new role you will: Develop and implement Design for Test (DFT) methodologies for IoT products. Collaborate with design and backend teams to integrate DFT features. Create and validate test plans to ensure thorough coverage and fault detection. Support silicon bring-up and debug activities. Automate test processes such as ATPG/MBIST to enhance ...

As a Design Verification Lead at Edveon, you will play a crucial role in the VLSI team in Chennai. Your responsibilities will include: - Leading end-to-end verification for complex SoC/IP projects - Developing UVM-based testbenches and verification environments from scratch - Driving functional and code coverage closure - Ensuring high-quality, first-time-right silicon through thorough validation - Collaborating with design, architecture, and validation teams To excel in this role, you should possess the following qualifications: - 7 to 15 years of experience in Design Verification - Strong hands-on expertise in SystemVerilog and UVM - Good understanding and working knowledge of RAL (Registe...

Key Responsibilities Develop comprehensive verification plans and strategies for SoC and GLS components. Design, implement, and maintain reusable testbenches using SystemVerilog and UVM methodologies. Perform functional verification of AMBA bus protocols including AXI, AHB, and APB. Collaborate with RTL designers and architects to understand specifications and implement verification environments accordingly. Analyze verification results, debug issues, and provide timely resolutions to meet project timelines. Ensure coverage goals are met through simulation and formal verification techniques. (Optional) Participate in DSP module verification to enhance verification scope. Mentor junior engine...

Role Overview: As an FPGA Design Engineer, you will be responsible for designing and implementing FPGA architectures using Verilog/VHDL. You will utilize advanced design techniques such as pipelining, data path optimization, and memory management to develop efficient solutions. Your understanding of network protocols, computer architecture, and high-speed digital design principles will be crucial in this role. Key Responsibilities: - Strong understanding of FPGA architecture and design methodologies - Implement advanced FPGA design techniques like pipelining and data path optimization - Familiarity with network protocols such as Ethernet, MPLS, and QoS - Knowledge of computer architecture an...

DV Engineer Experience : 1-3 years Location : Hyderabad Verilog, System verilog, UVM VHDL, UVVM 3rd party simulator exposure with VCS, Questa, Xcelium Proficient in simulation and HW languages Should be able to interpret various LRMs and comply with semantics and testcase creation. Interested,please drop your updated resume to [HIDDEN TEXT]

Key Responsibilities: Develop and execute verification test plans based on design specifications. Create constrained-random and directed testbenches using SystemVerilog/UVM. Develop functional coverage models and drive coverage closure. Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. Perform block-level and/or SoC-level verification. Integrate and verify 3rd-party IPs and custom IPs in subsystem and full-chip environments. Collaborate with RTL, DFT, DV, firmware, and physical design teams. Run regression simulations and ensure verification quality through coverage metrics. Automate verification flows and improve efficiency using scripting language...

Senior Design verification Engineer Mandatory Skill : PCIE Location : Bangalore Experience : 5 years Design Verification Engineer responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration: Work with RTL designers to identify and resolve design bugs. Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug. Protocols: Verify IP/SoC-level designs for common protocols ...

You will be responsible for developing FPGA designs using hardware description languages (HDLs) like VHDL or Verilog. Your tasks will include implementing and optimizing complex digital logic circuits for high-performance applications. Your duties will also involve performing synthesis, place and route, and optimization of FPGA designs to guarantee optimal area, performance, and power consumption. You will be expected to develop and execute testbenches for simulation and verification of FPGA designs using tools such as ModelSim, Vivado, or Questa. Your role will include ensuring that the designs meet functional, timing, and performance requirements.,

As a Team Leader in FPGA IP Verification, you will be responsible for leading and mentoring a team of engineers. You will define team priorities, set goals, and monitor performance through KPIs and regular reviews. Your role will involve fostering an environment of learning, collaboration, and technical excellence to enhance verification efficiencies. In terms of Technical Management, you will oversee the development and delivery of verification of IPs owned by the team, ensuring alignment with QPDS/releases. You will drive innovation in verification methodologies to enhance quality and efficiency. Collaboration with FPGA design, software, and validation teams to integrate IP into the Quartu...

Role & responsibilities Description: Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing and ...

Roles and Responsibilities Develop and maintain verification testbenches for SoC-level simulation and validation Create detailed verification plans based on design specifications and architectural documents Implement and run directed and constrained-random tests using SystemVerilog and UVM Debug RTL and gate-level simulations to identify and resolve design and testbench issues Contribute to regression testing, coverage analysis, and sign-off activities Work closely with cross-functional teams including design, DFT, and firmware engineers Support post-silicon bring-up and validation when required Requirements Strong experience in SystemVerilog and UVM for verification of digital designs Deep ...

As an Engineer (DFT) at eInfochips located in Bangalore, India, you will be responsible for hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in the usage of Synopsys tools such as DFT MAX and TetraMAX, as well as Cadence tools like RTL Compiler, Encounter Test, modus, and Janus. Additionally, experience with Mentor Graphics tools like Tessent tool chain, TestKompress, Debussy, VCS/Questa/IUS, and PT tool from Synopsys will be advantageous. This is a full-time position falling under the category of Engineering Services.,

Expertise in ASIC Verification of MAC protocols Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim , Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Co...

Looking for Siemens EDA ambassadors: Lead Software Engineer for Product Validation and Customer support for PowerPro If you are passionate about innovations that lead to real progress, and if you are curious about technologies that are yet to be developed, then this opportunity might be for you. Utilize your curiosity, passion, and creativity to enhance the lives of millions of people. Join us and share your unique perspective with us! As a valuable member of the Siemens EDA team, your role will involve contributing to the growth of efficiency and customer satisfaction within Siemens EDA's Power platform. This challenging position aims to support the expansion of Siemens's EDA business in In...

Lead Design Verification Engineer Bangalore We are looking for an experienced Lead Design Verification Engineer (412 yrs) to join our semiconductor team. Youll lead SoC/ASIC/IP verification using SystemVerilog, UVM, SVA, and drive test planning, coverage, regressions, and debug. ???? Must-have: Strong expertise in protocols (PCIe, DDR, USB, AMBA, MIPI, CXL), EDA tools (VCS, Xcelium, Questa), scripting (Python/Perl/Tcl), and low-power/CDC/formal verification. ???? Bonus: Experience with emulation/GLS, lint, DFT awareness, and leadership/mentoring. ???? Location: Bangalore, India ? Experience: 412 years ???? Apply now or share your profile at [HIDDEN TEXT] Show more Show less

As an experienced Verification Engineer with a minimum of 5 years of experience, your primary responsibility will be to lead the verification of DDR memory controller and PHY designs in compliance with DDR standards like DDR3, DDR4, DDR5, and other memory interface protocols. You will be required to develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM, and other industry-standard methodologies. Ensuring protocol compliance is crucial, which includes validating command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Your role will in...

As a Senior/Lead/Sr. Lead Design Verification Engineer at our company located in Bangalore or Hyderabad, you will play a crucial role in ensuring the verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need to have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 4 years of hands-on experience in this domain. Your responsibilities will include utilizing your expertise in SystemVerilog and UVM to develop verification components like scoreboards, monitors, and sequencers. You will be required to have a strong understanding of digital design principles, verification methodologies, and simulation tool...

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test...

As a Design Verification Engineer at our company, you will be responsible for verifying high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field along with at least 4 years of hands-on experience in design verification. Your role will require expertise in SystemVerilog and UVM (Universal Verification Methodology) as well as a strong understanding of digital design principles, verification methodologies, and simulation tools. It is essential for you to be familiar with protocol specifications and industry standards for the interfaces mentioned above. You should have experience workin...

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contri...