17 Questa Jobs

As a Team Leader in FPGA IP Verification, you will be responsible for leading and mentoring a team of engineers. You will define team priorities, set goals, and monitor performance through KPIs and regular reviews. Your role will involve fostering an environment of learning, collaboration, and technical excellence to enhance verification efficiencies. In terms of Technical Management, you will oversee the development and delivery of verification of IPs owned by the team, ensuring alignment with QPDS/releases. You will drive innovation in verification methodologies to enhance quality and efficiency. Collaboration with FPGA design, software, and validation teams to integrate IP into the Quartus ecosystem will be a key aspect of your responsibilities. Ensuring robust quality for the IP owned and providing technical guidance on verification methodology will also be part of your role. Your Functional Expertise will involve being a hands-on technical verification lead, owning the verification of IPs for FPGA. You will perform functional logic verification of an FPGA to ensure it meets specification requirements. Developing verification plans, test benches, and the verification environment to ensure coverage confirming to microarchitecture specifications will be crucial. Executing verification plans, defining and running simulation models, uncovering bugs, and replicating, root causing, and debugging issues in the pre-silicon environment will also be part of your duties. Additionally, collaborating with various teams and documenting test plans will be essential. Qualifications required for this role include a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. You should have 10+ years of experience in verification in IP/FPGA/SoC/ASIC domains and proven expertise in RTL design and verification for FPGA architectures. Hands-on experience with OVM/UVM, System Verilog, and constrained random verification methodologies is necessary. Familiarity with simulation tools such as ModelSim, Questa, VCS, or similar EDA simulators is essential. Experience with Ethernet/PCIe/PIPE & FPGA architecture is an added advantage. In terms of Leadership & Soft Skills, you should possess the ability to lead and develop technical teams, drive collaboration, and deliver results. Strong problem-solving and analytical skills with a proactive mindset are crucial. Excellent communication and stakeholder management skills, capable of engaging both technical and non-technical audiences, will be required. This job requires a proactive individual with strong technical skills, leadership capabilities, and excellent communication abilities. If you are passionate about leading a team in FPGA IP verification and driving technical excellence, this role could be the perfect fit for you.,

Role & responsibilities Description: Performs semiconductor design engineering assignments including engineering and designing chip layout circuits, circuit checking, documenting specifications, modifying and evaluating semiconductor devices and components. Reviews product requirements and logic diagrams for device definition. Typically responsible for projects, or portions of projects, to design, fabricate, modify, and evaluate semiconductor devices and components. 3-5 years of experience Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Experience with Gate Level Simulations and timing debugs. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Additional Details TSMC Certification:- Added Advantage

Roles and Responsibilities Develop and maintain verification testbenches for SoC-level simulation and validation Create detailed verification plans based on design specifications and architectural documents Implement and run directed and constrained-random tests using SystemVerilog and UVM Debug RTL and gate-level simulations to identify and resolve design and testbench issues Contribute to regression testing, coverage analysis, and sign-off activities Work closely with cross-functional teams including design, DFT, and firmware engineers Support post-silicon bring-up and validation when required Requirements Strong experience in SystemVerilog and UVM for verification of digital designs Deep understanding of SoC architecture, buses (e.g., AXI, AHB), and peripheral IPs Experience in writing test cases, assertions, and functional coverage models Familiarity with simulators such as VCS, Questa, or Incisive Hands-on experience with scripting languages like Python, Perl, or Shell for automation Exposure to version control and bug tracking tools Ability to analyze and debug waveform dumps and simulation failures

As an Engineer (DFT) at eInfochips located in Bangalore, India, you will be responsible for hands-on experience in various DFT aspects including Scan insertion, MBIST and JTAG, ATPG, and Pattern validation at both block level and Fullchip level. You will be proficient in the usage of Synopsys tools such as DFT MAX and TetraMAX, as well as Cadence tools like RTL Compiler, Encounter Test, modus, and Janus. Additionally, experience with Mentor Graphics tools like Tessent tool chain, TestKompress, Debussy, VCS/Questa/IUS, and PT tool from Synopsys will be advantageous. This is a full-time position falling under the category of Engineering Services.,

Expertise in ASIC Verification of MAC protocols Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim , Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath , DSP based ASICs Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory Good knowledge in gate-level simulation, and Scripting languages like Expertise in Python, TCL scripting

Looking for Siemens EDA ambassadors: Lead Software Engineer for Product Validation and Customer support for PowerPro If you are passionate about innovations that lead to real progress, and if you are curious about technologies that are yet to be developed, then this opportunity might be for you. Utilize your curiosity, passion, and creativity to enhance the lives of millions of people. Join us and share your unique perspective with us! As a valuable member of the Siemens EDA team, your role will involve contributing to the growth of efficiency and customer satisfaction within Siemens EDA's Power platform. This challenging position aims to support the expansion of Siemens's EDA business in India. You will be a part of the DDCP (Digital Design Creation Platform group), which encompasses renowned industry tools like Tessent, PowerPro, Catapult, and Aprisa. Operating within the DPRS (Devops, Product, Release & Support group) under DDCP, you will be focused on cutting-edge tools like PowerPro. Your responsibilities will revolve around Product Validation, Customer Support, and Release tasks for the PowerPro tool, a commercially available RTL sequential power optimization and power analysis tool. Join our energetic and passionate team driven by synergy and enthusiasm. **Key Responsibilities:** - Collaborate with the Product Validation and Customer Support team to validate and educate on the features of PowerPro. - Validate all features of the tool as an internal end-user, identify and report issues, develop test plans, write test cases, and enhance the product quality and test environment. - Assist in supporting and debugging customer test design methodologies using our products. - Engage in architecture reviews, contribute to defining feature prototypes, understand customer design flow requirements, and propose optimization measures. - Analyze customer-reported bugs, enhance testing procedures, incorporate new designs/flows, respond to customer inquiries using technical expertise, demonstrate products, and provide field application support to customers. - Lead and mentor 1-2 junior team members or interns, guiding them in their day-to-day activities. **Qualifications:** - B.Tech in Electrical/Electronics & Communication Engineering or M.Tech in VLSI/Microelectronics with 3+ years of relevant industry experience. - Profound knowledge of ASIC design flows, digital logic, and RTL/gate-level simulation and verification methodologies. - Proficiency in Verilog, VHDL, and SystemVerilog (SV). - Demonstrated understanding of low-power SoC design concepts, including power intent (UPF) and power-aware design methodologies. - Experience with simulation, synthesis, place & route tools and flows. - Hands-on expertise with industry-standard tools such as Power Artist, Joules, Prime Power/PTPX, Questa, VCLP, and Design Compiler (DC). - Proficiency in scripting languages like Perl and Tcl, with knowledge of Python being advantageous. - Strong problem-solving, debugging skills, and familiarity with RTL/gate-level simulation, emulation, SPEF, and various technology nodes. - Experience in EDA CAD support for RTL design teams is a plus. - Excellent communication skills, adaptable, collaborative, self-driven, and experienced in team leadership. Siemens is a global organization with over 377,000 individuals shaping the future in more than 200 countries. We are committed to equality and welcome applications that represent the diversity of the communities we serve. Employment decisions at Siemens are based on qualifications, merit, and business needs. If you bring curiosity, creativity, and the drive to shape tomorrow, we invite you to join us on this journey. Transform the everyday. Accelerate transformation. Hybrid.,

Lead Design Verification Engineer Bangalore We are looking for an experienced Lead Design Verification Engineer (412 yrs) to join our semiconductor team. Youll lead SoC/ASIC/IP verification using SystemVerilog, UVM, SVA, and drive test planning, coverage, regressions, and debug. ???? Must-have: Strong expertise in protocols (PCIe, DDR, USB, AMBA, MIPI, CXL), EDA tools (VCS, Xcelium, Questa), scripting (Python/Perl/Tcl), and low-power/CDC/formal verification. ???? Bonus: Experience with emulation/GLS, lint, DFT awareness, and leadership/mentoring. ???? Location: Bangalore, India ? Experience: 412 years ???? Apply now or share your profile at [HIDDEN TEXT] Show more Show less

As an experienced Verification Engineer with a minimum of 5 years of experience, your primary responsibility will be to lead the verification of DDR memory controller and PHY designs in compliance with DDR standards like DDR3, DDR4, DDR5, and other memory interface protocols. You will be required to develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM, and other industry-standard methodologies. Ensuring protocol compliance is crucial, which includes validating command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Your role will involve creating detailed verification plans based on DDR specifications and requirements, focusing on corner cases, timing, and protocol validation for full coverage. Running simulations, debugging issues using tools like Questa, VCS, or ModelSim, and applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage will be part of your daily tasks. You will set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues. Achieving high functional and protocol coverage is vital, ensuring that timing constraints, corner cases, and failure scenarios are thoroughly verified. Implementing formal verification techniques to validate critical components of the DDR design, ensuring correctness in timing and data flow, and verifying crucial operations will also be part of your responsibilities. This position requires a Bachelor's or Master's degree in ECE/EEE or VLSI/Electronics from a reputable institution. The position is based in Bangalore/Hyderabad.,

As a Senior/Lead/Sr. Lead Design Verification Engineer at our company located in Bangalore or Hyderabad, you will play a crucial role in ensuring the verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need to have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 4 years of hands-on experience in this domain. Your responsibilities will include utilizing your expertise in SystemVerilog and UVM to develop verification components like scoreboards, monitors, and sequencers. You will be required to have a strong understanding of digital design principles, verification methodologies, and simulation tools. Additionally, familiarity with protocol specifications and industry standards for DDR, PCIe, UCIe, or NVMe will be crucial for this role. Having experience with simulation tools such as VCS, ModelSim, or Questa will be an added advantage. You should also possess good debugging skills using tools like Waveform Viewers, Logic Analyzers, and protocol analyzers. Problem-solving skills, attention to detail, and the ability to work collaboratively are essential traits for this position. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, and proficiency in scripting languages like Python for automation purposes. Familiarity with FPGA-based verification platforms and hardware debugging tools will be beneficial in excelling in this role. If you are looking to join a dynamic team where you can leverage your skills in design verification and work on cutting-edge technologies, this position is ideal for you. Join us in our mission to push the boundaries of innovation and make a significant impact in the field of high-speed interface verification.,

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test-bench issues and failures. As part of this role, you will be accountable for verification closure by focusing on coverage and managing bug reports. Proficiency in utilizing industry-standard verification tools like Questa, VCS, or ModelSim is required. Experience with scripting languages like python, perl, or TCL for automation tasks is also beneficial. Furthermore, you will be responsible for managing a team of 6 to 7 Engineers and engaging with customers to provide task updates. Experience in collaborating with Japanese customers is a prerequisite for this position. Proficiency in the Japanese language is a mandatory skill. If you meet these qualifications and are enthusiastic about taking on these responsibilities, we encourage you to apply for this challenging and rewarding role.,

As a Design Verification Engineer at our company, you will be responsible for verifying high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field along with at least 4 years of hands-on experience in design verification. Your role will require expertise in SystemVerilog and UVM (Universal Verification Methodology) as well as a strong understanding of digital design principles, verification methodologies, and simulation tools. It is essential for you to be familiar with protocol specifications and industry standards for the interfaces mentioned above. You should have experience working with simulation tools like VCS, ModelSim, or Questa, and be proficient in debugging tools such as Waveform Viewers, Logic Analyzers, and protocol analyzers. The ability to write efficient and reusable verification components like scoreboards, monitors, and sequencers is crucial for this role. Strong problem-solving skills, attention to detail, and excellent communication skills are also required. You should be comfortable working in a collaborative environment and have a willingness to engage with team members effectively. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, proficiency in scripting languages for automation (e.g., Python), and familiarity with FPGA-based verification platforms and hardware debugging tools. If you are someone who enjoys working on challenging projects, has a passion for design verification, and meets the qualifications mentioned above, we would love to have you join our team in Bangalore or Hyderabad.,

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus" AMD (Dont Share AMD Profiles) Preferred candidate profile

Key Responsibilities: Develop and execute comprehensive verification plans for SoC and NoC systems Design and maintain test benches using SystemVerilog and UVM Perform functional, performance, and low-power verification Debug and resolve design/verification issues independently Work with high-speed protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe Ensure thorough coverage and compliance with design specifications Collaborate with cross-functional teams including RTL, DFT, and architecture Required Skills: 7+ years of hands-on experience in SoC/NoC verification Strong expertise in System Verilog, UVM, and scripting (Python/Perl/TCL) Experience with simulation tools like VCS, Questa, or Incisive Solid understanding of interconnect protocols: AXI, CHI, PCIe, Ethernet, etc. Familiarity with coverage analysis and debugging tools Strong analytical and problem-solving skills Preferred: Experience with CXL or UCIe protocols Exposure to formal verification or emulation tools is a plus

Job Specs : We are seeking a highly skilled and motivated ASIC Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Pune. Malaysia, Singapore Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering Visa / work permit sponsored for immediate hires Expertise in ASIC SOC verification Expertise in PCie Expertise in UVM, System Verilog and constrained random testing. Expertise in testbench architecture and SOC-level verification strategies. Expertise with protocols such as AXI, AHB, APB, USB, or DDR. Expertise with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa. Familiar with waveform debugging tools such as Verdi or DVE. Working knowledge of low-power verification (UPF) and DFT / scan concepts. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Job Specs : Develop and maintain full-chip verification environments using SystemVerilog UVM methodology. Define and execute test plans for SoC-level functionality, power intent (UPF), coherency, performance and interconnect protocols (e.g., AXI/ACE). Work closely with the RTL, DV, and integration teams to ensure complete coverage of functional and architectural features. Implement and manage stimulus generators, scoreboards, monitors, and checkers at full-chip level. Perform debugging, waveform analysis, and triage of failures in RTL simulations. Ensure code coverage and functional coverage goals are met and signoff criteria are satisfied. Collaborate with firmware/software and post-silicon teams to align verification efforts and resolve issues. Participate in formal verification, assertion-based verification, and low-power simulations. Support regression testing, issue tracking, and coverage closure. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. Expertise in ASIC SOC verification. Expertise in UVM, System Verilog and constrained random testing. Expertise in Gate Level Simulation tools (GLS) or verification related to display port or memory controller Expertise in testbench architecture and SOC-level verification strategies. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Preferred immediate hires only Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Bachelors or Masters degree in Electrical, Electronics or VLSI Engineering Expertise in DFX Verification preferred Expertise in DFT / ASIC Verification Expertise in System Verilog Expertise in UVM Expertise in python or perl scripting Expertise in verifying JTAG, scan chains, MBIST, LBIST, boundary scan and related test logic for large complex SoCs. Expertise in simulation tools like VCS, Questa, XSIM Excellent knowledge on RTL and DFT concepts Prior experience in Post-silicon validation is an added advantage Prior experience on automotive or AI SoCs is an added advantage Preferred resources with valid regional work permit

Key Responsibilities & Skills: • Expertise in UVM/OVM, testbench & simulation • Experience with AMBA, PCIe, MIPI, USB, Ethernet • Led team of 5+ engineers • Skilled in formal verification & Verilog • Independent & mentoring skills