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ASIC RTL Design Engineer

ASIC RTL Design Engineer

4 - 8 years

|

12 - 14 Lacs

Hyderabad

Posted:19 hours ago| Platform:

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Skills Required

axi rtl coding verilog lint logic design c++ semiconductor soc amba apb rtl design formal verification rtos asynchronous embedded systems soc design ahb protocols synthesis asic development asic mixed signal cdc rtl embedded system design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Required Skills

Experience in Logic design / RTL coding is a must.
Experience is SoC design and integration for complex SoCs is a must.
Experience in Verilog/System-Verilog is a must.
Experience in Multi Clock designs, Asynchronous interface is a must.
Experience in using the tools in ASIC development such as Lint and CDC.
Experience in Synthesis / Understanding of timing concepts is a plus.
Experience in ECO fixes and formal verification.
Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
Excellent oral and written communications skills.
Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

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MosChip

Semiconductors

Hyderabad

251-500 Employees

25 Jobs

Key People

M. S. V. Prasad

CEO
K. Srinivas Rao

CTO
Raghavendra Rao

Vice President of Sales

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