ASIC RTL Design Engineer

As an ASIC RTL Design Engineer with 5 to 8 years of experience, you will be responsible for applying your expertise in digital concepts and ASIC flow. Your primary focus will be on RTL coding, SoC design, and integration, utilizing your hands-on experience. Proficiency in Verilog/System-Verilog is a must, along with a solid understanding of AMBA protocols such as AXI, AHB, and APB. A basic understanding of verification principles is required for this role, while knowledge of Memory controller designs and microprocessors will be considered an advantage. Experience in Synthesis and a grasp of timing concepts will be beneficial. Strong communication skills, both oral and written, are essential in effectively collaborating with the team. Key Responsibilities: - Apply your knowledge of Verilog to RTL design and coding - Demonstrate expertise in ASIC flow and Static Timing Analysis (STA) - Collaborate with the team on synthesis and design aspects to ensure project success - Utilize your understanding of AMBA protocols to enhance SoC design - Continuously improve your skills and knowledge, contributing proactively to the team If you are a proactive, creative, curious individual who is motivated to learn and contribute effectively, this role offers an exciting opportunity to grow your career in ASIC design.,