ASIC RTL Design Engineer

You have a Job opportunity with eInfochips for the position of ASIC RTL DESIGN ENGINEERS based in Bangalore or Ahmedabad. **Role Overview:** You should have at least 5 years of experience in RTL design with expertise in Verilog/VHDL. Experience with simulation tools such as Modeslim/VCS and familiarity with basic protocols like I2C, UART, PCIe, and SPI are required. Knowledge of micro-architecture and CDC/Lint tools will be beneficial. Exposure to timing analysis, CDC design, and ISO26262 standards will be an added advantage. **Key Responsibilities:** - Experience in RTL design - Proficiency in Verilog/VHDL - Working with simulation tools like Modeslim/VCS - Understanding of basic protocols such as I2C, UART, PCIe, SPI - Knowledge of micro-architecture - Familiarity with CDC/Lint tools - Conducting timing analysis - Designing CDC - Exposure to ISO26262 standards - SOC integration **Qualifications Required:** - Minimum 5 years of experience in RTL design - Proficient in Verilog/VHDL - Familiarity with simulation tools like Modeslim/VCS - Understanding of basic protocols like I2C, UART, PCIe, SPI - Knowledge of micro-architecture - Experience with CDC/Lint tools - Ability to perform timing analysis - Exposure to CDC design - Knowledge of ISO26262 standards - Experience in SOC integration Kindly share your resume at medha.gaur@einfochips.com if you are interested in this position.,