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5.0 - 9.0 years
0 Lacs
karnataka
On-site
You have a Job opportunity with eInfochips for the position of ASIC RTL DESIGN ENGINEERS based in Bangalore or Ahmedabad. **Role Overview:** You should have at least 5 years of experience in RTL design with expertise in Verilog/VHDL. Experience with simulation tools such as Modeslim/VCS and familiarity with basic protocols like I2C, UART, PCIe, and SPI are required. Knowledge of micro-architecture and CDC/Lint tools will be beneficial. Exposure to timing analysis, CDC design, and ISO26262 standards will be an added advantage. **Key Responsibilities:** - Experience in RTL design - Proficiency in Verilog/VHDL - Working with simulation tools like Modeslim/VCS - Understanding of basic protocols ...
Posted 1 week ago
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