63 Microarchitecture Jobs

As a SoC Power Management Design Engineer at AMD, your role will involve developing and designing custom silicon for gaming consoles, datacenter, client, or embedded computer vision SOCs and related platforms. You will collaborate with the lead SoC architect to define customer-specific architectures, contribute to product specifications, and make performance and power trade-offs. Your work will span from early concept development through final production, requiring excellent organization and communication skills. You will work with expert architects and designers globally, presenting your findings to colleagues and customer engineering teams. Key Responsibilities: - Drive physical design and power architecture based on customer-specific requirements - Collaborate with AMD's Engineering teams and IP teams to aid in integration, implementation, and optimization of designs - Analyze power consumption and delivery using static, dynamic models, and emulation data - Evaluate performance across voltages for DVFS states of IPs, including inference engines, CPUs, Graphics, memory controllers, peripheral interfaces, caches, and network-on-chip fabric - Establish voltage-frequency design points in collaboration with technology teams, silicon validation, and product engineering teams - Define definitions for on-die PDN, power gating, package, and system power delivery in coordination with systems and architecture team - Analyze effects of control algorithms for management throttling mechanisms to optimize performance within thermal and peak current limits Preferred Experience: - Solid understanding of SoC construction, including fabric connectivity, memory systems, power delivery, clock distribution, floor planning, and packaging - Strong knowledge of SoC power management, power dissipation, and mobile battery life - Proficiency in scripting, data analysis, EDA tools, physical design tools for power optimization, VLSI design flow, and CMOS technology - Ability to model thermal control loops and throttling mechanisms - Strong problem-solving, organizational, and communication skills with the ability to work in a dynamic and diverse environment - Proficiency in scripting languages, particularly Python, is highly preferred - Experience with Power Architect, Power Artist, and VisualSim is a plus - Detail-oriented thinking skills and ability to tackle novel problems from different perspectives and levels of abstraction - Capability to analyze and streamline sophisticated workflows and processes through innovative automation Academic Credentials: - Bachelors or Masters degree in computer engineering/Electrical Engineering (Note: The benefits offered are described separately in the AMD benefits overview.),

As an experienced ASIC RTL Design Engineer at MarvyLogic, you will be responsible for designing cutting-edge solutions that impact various industries. Your role will involve working with multiple clock and power domains, integrating and validating MIPI cores, debugging, and implementing CSI/DSI controllers. Your expertise in Verilog/System Verilog will be crucial in creating micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance with coding standards. Additionally, you will play a key role in the design verification and physical implementation processes to meet performance goals. **Key Responsibilities:** - Utilize your 10+ years of ASIC RTL Design experience to develop innovative solutions - Demonstrate proficiency in Verilog/System Verilog and experience with multiple clock and power domains - Integrate and validate CSI/DSI/DPHY/CPHY/other MIPI cores, including controllers and SerDes - Debug CSI/DSI issues and design and implement CSI/DSI controllers - Create block-level micro-architecture specifications outlining interfaces, timing behavior, and design tradeoffs - Review vendor IP integration guidelines and ensure compliance throughout the design flow - Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to meet coding and implementation guidelines - Participate in design verification and physical implementation processes to achieve area, power, and performance goals **Qualifications Required:** - 10+ years of ASIC RTL Design experience - Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus) - Experience with CSI/DSI debug and FPGA netlist releases - Familiarity with ASIC product life cycle (requirements, design, implementation, test, and post-silicon validation) - Strong communication skills and ability to collaborate with multi-site teams At MarvyLogic, we foster a culture that values passion for technology solutions and individual growth. Working with us will provide you with exposure to diverse industries and emerging technologies, helping you evolve both professionally and personally towards a more fulfilling life.,

As an experienced ASIC/FPGA digital designer with 7-10 years of experience, you will be responsible for the following key responsibilities: - Utilize your expertise in Verilog/VHDL, Micro-architecture, and RTL Implementation to contribute to the development of cutting-edge technology. - Apply your knowledge in USB, PCIe, and Ethernet domains to design and implement efficient solutions. - Utilize tools such as Synopsys/Cadence Synthesis/STA tools and FPGA to optimize performance and functionality. - Proficiency in scripting skills will be an added advantage in enhancing the design process. Qualifications required for this role include: - BE in Electronics & Communication Engineering In addition to the above, Microchip Technology, Inc. offers a supportive work environment where you can be a part of a dedicated team that challenges the status quo and empowers innovation. With over 30 years of quarterly profitability, our company values employee development, values-based decision making, and a strong sense of community. Join us to be a part of a multi-billion dollar global organization that fosters career growth and stability. Please note that Microchip Technology Inc. does not accept unsolicited agency resumes and is not responsible for any fees related to unsolicited resumes.,

As a Design Engineer-2 FPGA Architecture at Lattice Semiconductor, you will be part of a dynamic team focused on FPGA architecture modeling and system architecture advancements. You will have the opportunity to contribute, learn, innovate, and grow within a fast-paced, results-oriented environment. Your responsibilities will include working in RTL design, utilizing best-in-class coding styles, algorithms, and both Verilog and System Verilog. You will be involved in architecture modeling and evaluation of Lattice FPGAs and Software tools to measure performance, power, and area for various workloads. Additionally, you will drive subsystem development, ensuring designs meet high standards of quality and reliability while working closely with the Software tools team. As a key contributor, you will build FPGA architecture modeling and evaluation platform efforts, drive logic design of key FPGA workloads, and develop regression testing frameworks to accelerate design and test time and quality. You will also be responsible for conducting regular reviews and audits to ensure design quality throughout project development. To excel in this role, you should possess a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent, along with at least 3 years of experience in driving logic design across various FPGA projects. Expertise in FPGA designs, micro-architecture definition, and experience with EDA tools is essential. You should have proven abilities to work with multiple groups across different sites and time zones, be an independent worker and leader with excellent problem-solving skills. If you are enthusiastic about FPGA technology, enjoy collaborating with diverse teams, and are eager to contribute to the advancement of programmable logic solutions, then this position at Lattice Semiconductor might be the perfect fit for you.,

As a member of our team, you will play a key role in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. You will be at the forefront of innovation, contributing to products that are cherished by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. In your role within the platform IP team, you will be involved in designing foundation and chassis IPs for Pixel SoCs, including components such as NoC, Clock, Debug, IPC, MMU, and other peripherals. Collaboration with cross-functional teams such as architecture, software, verification, power, timing, and synthesis will be essential as you specify and deliver RTL solutions. Your problem-solving skills will be put to the test as you tackle technical challenges using innovative micro-architecture and low-power design methodologies, assessing design alternatives based on complexity, performance, and power considerations. Google's overarching mission is to organize the world's information and make it universally accessible and useful. Our team leverages the synergies between Google AI, Software, and Hardware to create exceptionally beneficial user experiences. Through our research, design, and development efforts, we strive to enhance computing speed, seamlessness, and power. Ultimately, our goal is to enhance people's lives through technology. Your responsibilities will include defining microarchitecture specifics such as interface protocols, block diagrams, data flow, and pipelines. You will engage in RTL development using SystemVerilog, conducting and debugging functional and performance simulations. Additionally, you will be responsible for performing RTL quality checks, including Lint, CDC, Synthesis, and UPF checks. Participation in synthesis, timing/power estimation, and FPGA/silicon bring-up processes will also be part of your role. Effective communication and collaboration with diverse, geographically dispersed teams will be essential for success in this position.,

Responsibilities: * Collaborate with cross-functional teams on microarchitectural design and optimization. * Develop RTL code using System Verilog and ARM processors.

You have a passion for leading edge CPU/SoC architecture, design and verification. You are a team player who has excellent communication skills and enjoys collaborating with architects engineers located in different sites and time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Work with CPU micro-architects and designers to optimize future CPU cores Analyze the competition and identify areas for future improvement in our products Characterize workloads, project performance, and debug performance problems Run performance simulations and analyze results to evaluate CPU architectural features Enhance existing application tracing techniques Develop and maintain tools for data collection and analysis Execute post-silicon debug/tuning efforts to ensure AMD processors are fully performance optimized Job responsibilities also include multi-discipline interactions with microprocessor architects, ISA definition owners, software optimizers, compiler team, logic designers, and verification engineers to identify, resolve and document architectural performance issues PREFERRED EXPERIENCE: 3-15years of prior industry/academic experience Strong experience with computing software, including operating systems, hypervisors, compilers, drivers, and applications Experience with computer architecture, system simulation, and performance evaluation Experience analyzing system bottlenecks and optimizing computing systems for performance Adept at mathematical and statistical modeling Experienced with x86 instruction set processors Proficient in C/C++ programming and software engineering concepts

As a candidate for this role, you will have the opportunity to work directly with customers in the development of RTL code, quality checks, and bug fixing. You should possess 4-7 years of experience and be well-versed in micro-architecture and design of digital IPs and subsystems. Your responsibilities will include understanding the RTL design and microarchitecture of IPs, integrating them into sub-systems, defining SoC IP architecture, and developing RTL. In this position, you will be responsible for conducting RTL Quality Checks such as Clock Domain Crossing (CDC) check, Lint, Design for Testability (DFT) checks, Low Power Checks, as well as RTL Synthesis and STA support. Your expertise in these areas will be crucial to ensuring the quality and functionality of the digital IPs and subsystems. Overall, this role will require a strong background in RTL design, microarchitecture, and quality assurance processes. If you are a detail-oriented individual with a passion for digital design and a proven track record in RTL development, we encourage you to apply for this exciting opportunity.,

The ideal candidate for this role should hold a Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field or possess equivalent practical experience. Additionally, you should have at least 5 years of experience working with ML/AI frameworks and libraries such as TensorFlow, PyTorch, and scikit-learn. It is essential to have a background in hardware description languages like Verilog, SystemVerilog, and VHDL, along with experience in applying ML/AI techniques. Preferred qualifications include hands-on experience with ML/AI applications in hardware design, verification, and Low Power, such as formal verification with ML and coverage closure with ML. Familiarity with verification methodologies like UVM and OVM is highly advantageous. Proficiency in data preprocessing, feature engineering, hardware architecture, microarchitecture, and simulation tools like Synopsys VCS, Cadence Xcelium, and Mentor Questa is preferred. Excellent programming skills in Python or C++ are also desirable. As a member of our team, you will be part of a group that continually pushes boundaries by developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a crucial role in innovating products that are adored by millions worldwide, shaping the next generation of hardware experiences to deliver unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team leverages the best of Google AI, Software, and Hardware to create incredibly helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include researching, designing, and implementing ML/AI algorithms and techniques for various verification tasks, such as test case generation, coverage analysis, bug prediction, and performance optimization. You will be tasked with developing and maintaining tools and scripts for data collection, preprocessing, model training, and evaluation. Additionally, you will analyze large datasets of simulation results, logs, and other verification data to identify patterns and trends, building and training ML models for various verification applications, and evaluating model performance to enhance accuracy and efficiency. Furthermore, you will participate in verification planning, developing test plans that integrate ML/AI-driven techniques, executing verification tests, and analyzing results to pinpoint bugs and coverage gaps. You will also be responsible for developing and maintaining verification tools and scripts to automate verification tasks effectively.,

Alternate Job Titles: ASIC Digital Design, Staff Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and experienced digital design engineer with a deep-rooted curiosity for advancing technology. With a strong foundation in RTL coding, microarchitecture, and high-speed digital IP, you thrive on tackling complex engineering challenges and delivering robust, scalable solutions. You are comfortable navigating the nuances of cutting-edge SERDES IP development and enjoy collaborating with cross-functional teams to deliver industry-leading results. Your proactive nature keeps you ahead of the curve, and your keen problem-solving abilities allow you to identify and resolve issues swiftly. You communicate effectively, ensuring your ideas are heard and understood, and you take pride in mentoring peers and contributing to a culture of continuous learning. You value diversity, demonstrate adaptability in a fast-paced environment, and bring both creativity and discipline to your work. Your technical acumen is matched by your drive to innovate, automate, and optimize design flows, making you an invaluable asset to any team focused on delivering world-class silicon solutions. What Youll Be Doing: Analyzing and understanding complex IP specifications, clock architectures, and interface requirements for high-speed SERDES IP. Designing, implementing, and optimizing Verilog RTL code to meet stringent performance, area, and power goals. Debugging and verifying advanced digital features to ensure functional correctness and compliance with industry standards Developing and automating design flows and scripts using Perl, Tcl, or Python to enhance productivity and streamline processes. Collaborating with cross-functional teams, including analog, verification, and validation groups, to resolve technical challenges creatively. Participating in design reviews, providing technical leadership, and contributing to best practice methodologies for digital IP development. Staying current with industry trends and integrating innovative techniques into the design and verification process. The Impact You Will Have: Enable the delivery of next-generation high-speed SERDES IP that powers a diverse range of customer products. Drive innovation in digital design methodologies, boosting design efficiency and product quality. Ensure Synopsys DesignWare IP remains at the forefront of performance, reliability, and feature support in the global market. Facilitate seamless integration of IP into customer SoC designs, accelerating time-to-market for industry leaders. Mentor and uplift the technical capabilities of team members, fostering a culture of collaboration and excellence. Contribute to Synopsys' reputation as a trusted partner for silicon-proven, high-performance IP solutions. Support continuous improvement by identifying and implementing process and technology enhancements. What Youll Need: Bachelors or Masters degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. 6 to 10 years of hands-on experience in high-speed digital IP design, particularly for SERDES or similar interfaces. Expertise in microarchitecture, RTL coding (Verilog), and debugging complex digital designs. Proficiency with industry-standard EDA tools and design flows for digital implementation and verification. Strong scripting skills in Tcl, Perl, or Python for flow automation and process enhancement. In-depth understanding of timing analysis, clock domain crossing, and interface protocols. Who You Are: Analytical thinker with excellent problem-solving and debugging skills. Proactive, self-motivated, and eager to take initiative in challenging situations. Exceptional communicator who thrives in a collaborative, cross-functional team environment. Committed to continuous learning, embracing new tools, techniques, and industry trends. Adaptable, resilient, and able to manage multiple priorities in a fast-paced setting. Values diversity, inclusion, and a culture of mutual respect. The Team Youll Be A Part Of: You will join a world-class team of digital and mixed-signal engineers focused on developing high-speed SERDES IP, a cornerstone of the Synopsys DesignWare portfolio. Our team values innovation, collaboration, and technical excellence. We work closely with specialists across analog, verification, validation, and customer support to deliver robust, scalable IP solutions that meet the highest standards of quality and performance. Youll have the opportunity to collaborate with experts in the field, contribute to groundbreaking projects, and help shape the future of silicon technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

As an experienced professional in ASIC development with a background in Electrical Engineering, Computer Engineering, or related fields, you will play a crucial role in shaping the future of AI/ML hardware acceleration. Your primary responsibility will be to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. Working within a dynamic team environment, you will contribute to the innovation behind products loved by millions worldwide, focusing on verifying complex digital designs with a specific emphasis on TPU architecture and its integration within AI/ML-driven systems. Your role will also involve collaborating with cross-functional teams to design ASICs that enhance traffic efficiency in data centers. By leveraging your expertise in micro-architecture and logic solutions, you will be responsible for specifying and delivering quality designs for next-generation data center accelerators. Additionally, you will lead a team of Engineers in the design organization to deliver IPs or Subsystems, drive feature closure, and develop microarchitecture specifications in alignment with Architecture, Firmware, and Software teams. The ML, Systems, & Cloud AI (MSCA) organization at Google focuses on designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. As a member of this team, you will be at the forefront of driving innovation and shaping the future of hyperscale computing. Your contributions will prioritize security, efficiency, and reliability across all projects, from developing the latest TPUs to managing a global network. Your key responsibilities will include leading a team of Engineers, owning microarchitecture and implementation of IPs and subsystems in the networking domain, collaborating with cross-functional teams, driving design methodology enhancements, and identifying opportunities for Power, Performance, and Area improvements within the domains you oversee.,

As a GPU Design and micro-Architect at Qualcomm India Private Limited, you will be responsible for collaborating across functions like GPU architecture and Systems to design and develop the next generation GPU features. Your key responsibilities will include working closely with Architecture teams to create micro-architecture and hardware specifications for features, taking ownership of design and RTL, reviewing test plans with Design Verification teams, and ensuring validation of all design features across products. Additionally, you will collaborate with physical design teams to optimize power, performance, and area metrics for the GPU blocks. Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of Hardware Engineering or related work experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 5+ years of Hardware Engineering or related work experience OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering or related work experience Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm via email at disability-accomodations@qualcomm.com or call the toll-free number provided on the Qualcomm website. Reasonable accommodations will be provided to support individuals with disabilities in participating in the hiring process. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and the protection of confidential information. The company is dedicated to making the workplace accessible for individuals with disabilities. Note to Staffing and Recruiting Agencies: Qualcomm's Careers Site is intended for individuals seeking employment directly with Qualcomm. Staffing and recruiting agencies, as well as individuals represented by an agency, are not authorized to use the site or submit profiles, applications, or resumes. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not consider unsolicited resumes or applications. For inquiries about specific roles, please contact Qualcomm Careers directly.,

Positions are open for immediate Co-op/internship(6 months or more duration) in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal. We are looking for all levels of talent, from entrance to advanced level of experience. Responsibilities Work closely with architecture and RTL designers on verifying the functionality correctness of the design Reviewing Architecture and Design Specifications Develop test plans and test environments Develop tests in assembly, C/C++, or vectors according to test plans Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered Develop checkers in SystemVerilog or C-base transactors to verify the design Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests Debugging failures, running simulations, tracking bugs Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions Requirements In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture. Sophisticated knowledge of SystemVerilog. Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection. Basic knowledge of formal verification methodology is a plus. Excellent knowledge of one of the scripting languages such as Python, TCL is a plus. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education And Experience PhD, Masters Degree or Bachelors Degree in technical subject area. Show more Show less

You are a seasoned Microarchitect and RTL Design Engineer with a strong background in microarchitecture and RTL coding. Your main responsibility will be to design and develop microarchitectures for a set of highly configurable IPs, ensuring optimal performance, power, and area. You will collaborate with software teams to define configuration requirements, verification collaterals, and work with verification teams on assertions, test plans, debug, coverage, etc. To qualify for this role, you should have a BS or MS in Electrical Engineering, Computer Engineering, or Computer Science along with 8+ years of current hands-on experience in microarchitecture and RTL development. Proficiency in Verilog, System Verilog, familiarity with industry-standard EDA tools and methodologies, and experience with large high-speed, pipelined, stateful designs, and low power designs are required. You should also have an in-depth understanding of on-chip interconnects and NoC's, experience within Arm ACE/CHI or similar coherency protocols, and experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoC's. Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus, as well as experience with modern programming languages like Python. Your problem-solving skills, attention to detail, communication, and collaboration skills should be excellent to excel in this role.,

You will be part of a highly skilled and challenging high-speed parallel PHY design team, working on interfaces such as DDR, LPDDR, etc. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as high-speed data paths, analog calibration, training, IP initialization, low power control, test, loopback, etc. You will be accountable for various aspects of design and verification from specification to silicon, as well as interface design for the controller and SoC. Your role will also involve active participation in problem-solving and implementing opportunities for improvement. Additionally, you will mentor and coach other design team members on technical issues and collaborate with Analog designers to ensure a smooth interface between Digital and Analog circuits. Your skills should include a strong fundamental knowledge of digital design, Verilog, and scripting languages. Experience with micro-architecture and Asynchronous digital designs is required. You should have a working knowledge of Synthesis, STA, Lint & CDC, as well as DDR/LPDDR JEDEC protocol and DDR PHY designs. Experience with DDR training algorithms and data path designs is essential, along with expertise in domain transfer designs, APB/JTAG, DFI. A degree in M.S./M.Tech or BS/BE (Electronics) is preferred with a minimum of 7 years of experience. Micron Technology is a global leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. With a focus on technology leadership, manufacturing excellence, and customer satisfaction, Micron delivers a diverse portfolio of high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. The innovations created by Micron's team drive the data economy, enabling advancements in artificial intelligence and 5G applications across various platforms. For more information, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, you can contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all applicable laws, regulations, and international labor standards.,

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture, and automation, you are well-equipped to excel in this role. Additionally, you should have 3 years of experience with Register-Transfer Level quality check tool flows such as Lint, Clock Domain Crossing, Reset Domain Crossing, and Synthesis. Preferred qualifications include experience with methodologies for RTL quality checks, IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols, and ASIC methodology. Additionally, experience with methodologies for low power estimation, timing closure, synthesis, and knowledge in areas such as Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin Multiplexing would be advantageous. Your responsibilities will involve defining microarchitecture details for the integration of Intellectual Property's (IPs) at the macro/Sub-System Workload Requirements Plan (SSWRP) level. You will be engaged in RTL development using SystemVerilog, debugging functional/performance simulations, and conducting RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, and Unified Power Format (UPF) checks. Furthermore, you will participate in synthesis, timing/power estimation, and FPGA/silicon bring-up processes. Join us in our mission to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create experiences that are radically helpful. By researching, designing, and developing new technologies and hardware, we aim to make computing faster, seamless, and more powerful, ultimately improving people's lives through technology.,

As a Senior ASIC RTL Design Engineer at Google, you will play a crucial role in shaping the future of custom silicon solutions that drive Google's direct-to-consumer products. Your expertise in RTL design will be instrumental in delivering innovative hardware experiences with superior performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience, and a minimum of 15 years of experience in ASIC RTL design, you are well-equipped to excel in this role. Your proficiency in Verilog/System Verilog and microarchitecture will be essential in contributing to the development of ARM-based SoCs, interconnects, and ASIC methodology. In addition to your technical skills, having a Master's degree in Electrical Engineering or Computer Engineering will be advantageous. Your experience in driving multi-generational roadmaps for IP development and leading interconnect IP design teams for low power SoCs will further enhance your capabilities. As part of our dynamic team, you will lead a group of talented individuals to deliver fabric interconnect design. Your responsibilities will include developing and optimizing RTL designs to meet power, performance, area, and timing requirements. You will define key details such as interface protocols, block diagrams, data flow, and pipelines while overseeing RTL development and conducting functional/performance simulations. Effective communication and collaboration with cross-functional and multi-site teams will be crucial in ensuring the successful execution of projects. By joining Google's Devices & Services team, you will have the opportunity to contribute to creating revolutionary technologies that enhance user experiences and make a positive impact on people's lives through cutting-edge hardware innovations.,

As a candidate for this role, you should hold a Bachelor's degree in Electrical/Computer Engineering or possess equivalent practical experience. You should also have at least 2 years of experience working with RTL design using Verilog/System Verilog and microarchitecture, particularly in the realm of ARM-based SoCs, interconnects, and ASIC methodology. A Master's degree in Electrical/Computer Engineering would be considered a preferred qualification for this position. Additionally, experience with methodologies for RTL quality checks (such as Lint, CDC, RDC) and low power estimation, timing closure, and synthesis would be beneficial. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that will power the future of Google's direct-to-consumer products. Your contributions to this team will play a crucial role in shaping the innovation behind products that are beloved by millions around the globe. Your expertise will be instrumental in defining the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration. Within our platform IP team, you will collaborate on designing foundation and chassis IPs for Pixel SoCs, including components such as NoC, Clock, Debug, IPC, MMU, and other peripherals. Your role will involve partnering with colleagues from various disciplines including architecture, software, verification, power, timing, and synthesis to specify and deliver RTL. You will be tasked with solving technical challenges using innovative micro-architecture, implementing low power design methodologies, and assessing design options based on complexity, performance, and power considerations. At Google, our mission is to organize the world's information and make it universally accessible and useful. By combining the strengths of Google AI, Software, and Hardware, our team strives to create profoundly helpful experiences. We engage in research, design, and development of new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately aiming to improve people's lives through technology. Your responsibilities in this role will include defining microarchitecture details such as interface protocols, block diagrams, data flow, and pipelines. You will be involved in RTL development using SystemVerilog, debugging functional and performance simulations, conducting RTL quality checks (including Lint, CDC, Synthesis, UPF checks), participating in synthesis, timing/power estimation, and FPGA/silicon bring-up, as well as collaborating with multidisciplinary teams across different locations.,

Description We are seeking an experienced Data Analyst to join our team in India. The ideal candidate will have 5-15 years of experience in data analysis, with a strong ability to derive insights and contribute to data-driven decision-making. Responsibilities Analyze and interpret complex data sets relating to the business. Develop and maintain reports, dashboards, and data visualizations. Collaborate with cross-functional teams to understand data requirements and provide insights. Identify trends, patterns, and insights to drive business decisions. Assist in the implementation of data collection systems and other strategies that optimize statistical efficiency and data quality. Skills and Qualifications Proficiency in SQL and experience with database management systems. Strong knowledge of data visualization tools (e.g., Tableau, Power BI, or similar). Experience with statistical analysis software (e.g., R, Python, SAS, or similar). Familiarity with data warehousing concepts and ETL processes. Excellent analytical and problem-solving skills. Strong attention to detail and ability to work with large data sets. Effective communication skills to present findings to stakeholders.

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime is necessary. An understanding of constraint development and timing closure will be a plus. Experience in Synthesis and knowledge of timing concepts will also be beneficial. Additionally, experience in creating padring and collaborating with the chip-level floorplan team is desirable. You must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of relevant experience will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities in the hiring process. The company expects all employees to adhere to relevant policies and procedures, including security protocols and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers.,

MIPS is looking for a highly experienced and motivated Engineering Manager to lead the CPU team. In this critical role, you will manage a team of skilled engineers dedicated to developing high-performance CPU cores based on the RISC-V architecture. Your responsibilities will include overseeing the entire RTL design lifecycle, ensuring technical excellence, innovation, and timely delivery. You will lead and mentor a team of microarchitecture and RTL design engineers focused on high-performance CPU core development. Your role will involve driving the design execution of CPU subsystems, meeting performance, power, area, and quality goals. You will be responsible for creating and refining microarchitecture specifications and RTL designs for CPU core components, collaborating with various teams to ensure efficient implementation, optimizing design methodologies for scalability and quality, and fostering a culture of innovation and technical excellence. The ideal candidate should have a Master's or PhD in Electrical Engineering, Computer Engineering, or a related field, with at least 15 years of experience in silicon or CPU design, including 5+ years in a management role. A proven track record of successfully delivering complex CPU blocks or subsystems, deep understanding of microprocessor design principles, strong technical knowledge in RTL design, and experience with project management and organizational skills are required. Preferred qualifications include experience with RISC-V, MIPS, or ARM CPU cores, familiarity with advanced CPU design concepts, working in a globally distributed environment, proficiency with EDA tools and scripting languages, and modern design methodologies. Joining MIPS offers you the opportunity to work with a dynamic and fast-growing team that is shaping the future of high-performance RISC-V processors. With small, agile teams and a flat organizational structure, you will have a direct impact on cutting-edge technology and product direction. MIPS provides an autonomous and empowering work culture, the chance to collaborate with industry-leading engineers, competitive compensation and benefits, and a platform for career growth in the exciting RISC-V ecosystem.,

You will provide technical leadership in conceptualizing and architecting the frontend digital design of products at Cadence. Your role will involve defining micro-architecture and driving successful implementation. Additionally, you will mentor and guide the team, drive processes, and design principles to achieve high-quality designs and PPA. You are expected to stay updated with standard specifications, develop insights into customer requirements and PPA trends, and contribute to defining the product feature roadmap. Your experience should include involvement in product development from concept to silicon, allowing you to provide technical support across cross-functions and contribute to pre-sales and customer enablement activities. Join Cadence to make an impact on the world of technology by solving challenges that others cannot.,

This role is for an IP / SoC RTL Senior / Lead Design Engineer to be responsible for the development and integration of IP and sub-systems. The ideal candidate will have strong expertise in logic design, RTL coding, and ASIC development, with a focus on creating high-performance, complex digital designs. Responsibilities Responsible for IP / sub-system level micro-architecture development and RTL coding . Prepare block/sub-system level timing constraints . Integrate IP/sub-system into larger designs. Perform basic verification in either an IP verification environment or on an FPGA. Skills Expertise in Verilog is a must. Experience in Logic design, micro-architecture, and RTL coding is essential. Knowledge of AMBA protocols - AXI, AHB, APB . Experience in synthesis and a strong understanding of timing concepts for ASIC development. Hands-on experience in multi-clock designs and asynchronous interfaces is a must. Experience with tools used in all phases of ASIC development, such as Lint, CDC, and Simulation . Knowledge of low power concepts is a plus. Experience in designing controllers for complex protocols like DDR, USB, or PCIe is a plus. Qualifications B.Tech. or M.Tech. with relevant experience. Immediate availability is preferred

NVIDIA has a rich history of over 25 years in transforming computer graphics, PC gaming, and accelerated computing through innovative technology and exceptional individuals. The company is currently leveraging the potential of AI to shape the next era of computing, where GPUs serve as the central intelligence of various devices like computers, robots, and self-driving cars. To achieve groundbreaking milestones, NVIDIA seeks individuals with a vision, a drive for innovation, and a commitment to excellence. As an NVIDIAN, you will be part of a diverse and supportive environment that fosters creativity and encourages top-notch performance. Join us to be a catalyst for change and create a lasting impact on the world. Currently, we are seeking RTL Design engineers to work on the Security Subsystem Design deployed in Automotive, GPU, DPU, and Client chips. In this role, you will play a key part in designing the Security cluster for the next generation of chips. The ideal candidate should have a solid foundation in digital design and verification principles. Your responsibilities will include: - Understanding system security concepts and features - Making architectural decisions based on performance, power, and feature requirements - Analyzing system implications and defining micro-architecture - Implementing RTL, driving verification, closing timing, and supporting silicon validation - Owning micro-architecture and RTL development of design modules - Micro-architecting features to meet performance, power, and area requirements - Collaborating with HW architects to define critical features - Partnering with verification teams to ensure feature correctness - Working with timing, VLSI, and Physical design teams to meet design requirements We are looking for candidates who possess: - A BTech/MTech degree with a proven track record in crafting complex Units and CPU/micro-controller based Sub-systems - 2+ years of design experience - Knowledge of security standards, protocols, and system security architectures of modern SOC's would be a plus - Excellent influencing skills for collaboration with diverse teams - Strong debugging, analytical, and problem-solving abilities - Outstanding interpersonal skills and a team-player mindset At NVIDIA, we have a team of brilliant and talented individuals who are passionate about technology and driving innovation. If you are a creative, independent thinker with a genuine passion for advancing technology, we would like to hear from you. NVIDIA is renowned as one of the most sought-after employers in the technology industry, offering competitive salaries and a comprehensive benefits package. Explore the opportunities we have for you and your family at www.nvidiabenefits.com/.,

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,