37 Microarchitecture Jobs

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, and Physical Layer Device, you are well-equipped to excel in this role. Proficiency in Verilog or SystemVerilog language is a must to thrive in this dynamic environment. Ideally, you possess experience in high-performance design, multi-power domains with complex clocking, and have a proven track record of delivering successful SoCs. Your expertise in microarchitecture design and system design will be pivotal in developing highly optimized IPs with excellent Power, Performance, and Area (PPA) metrics. Familiarity with chip design flow and quality checks at the front end, including Lint, CDC/RDC, Synthesis, and Line Echo Cancellation, will further enhance your capabilities. In this role, you will lead a team of RTL engineers, overseeing IP development plan tasks, conducting code and design reviews, and driving the development of complex features within the IP. Collaboration with the architecture team is essential to strategize microarchitecture and coding implementations that align with quality, schedule, and PPA goals. Additionally, you will work closely with cross-functional teams, including Verification, Design for Test, Physical Design, and Software teams, to make informed design decisions and ensure project progress is effectively communicated throughout the development lifecycle. Join our diverse team of passionate individuals who are committed to pushing boundaries and creating innovative solutions that enhance the lives of people globally. Together, we aim to make technology faster, seamless, and more powerful, ultimately realizing Google's mission of organizing the world's information and making it universally accessible and useful.,

We are seeking a highly skilled Physical Design Engineer to own the RTL to GDS physical implementation flows for high-performance and low-power designs. You will be responsible for synthesis, floor-planning, place and route, clock tree synthesis, timing and power closure, EM/IR, PDV, and final PD sign-off. This role requires deep collaboration with micro-architects, expertise in physical design tools, and a strong understanding of modern sub-micron technology nodes. Roles and Responsibility: Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV, and final PD sign off. Own physical design & implementation of high-performance designs from block level to system level components. Deep collaboration with Micro-architects to explore performance, power and area (PPA) trade-offs for high performance and low power designs. Conduct physical implementation feasibility studies and provide design recommendations for best PPA. Develop methodologies and recipes for various stages of physical implementation. Perform various physical design validation (PDV) flows for Timing, Power, EM/IR, etc., to ensure physical design quality. Perform design rule checking (DRC), LVS (Layout Versus Schematic) checks , and other physical verification tasks. Qualifications and Preferred Skills: Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure, EM/IR, physical design validation, etc. Experience with synthesis, place & route, static timing analysis and PDV tools . Experience in implementing clock trees and power grids . Experience with scripting for physical design flow automation . Experience with Synopsys tools such as Design Compiler, Prime Time, ICC, Fusion Compiler , etc. Good knowledge of high-performance and low-power microarchitecture and logic design principles . Understanding of modern ( sub 7nm ) sub-micron technology nodes and device physics. Basic knowledge of System/SoC Architecture and System Verilog RTL coding. Strong communication and collaboration skills. QUALIFICATION: BS, MS in Electrical Engineering or Computer Engineering or related degree.

We are seeking a highly skilled Microarchitect and RTL Design Engineer to design and develop microarchitectures for highly configurable IPs, ensuring optimal performance, power, and area. You will collaborate with software and verification teams on various aspects of the design lifecycle, from defining configuration requirements to debugging and coverage. This role requires extensive hands-on experience in microarchitecture and RTL development, proficiency in Verilog/SystemVerilog, and an in-depth understanding of on-chip interconnects and NoCs. Roles and Responsibilities: Design and develop microarchitectures for a set of highly configurable IPs. Perform microarchitecture and RTL coding , ensuring optimal performance, power, and area. Collaborate with software teams to define configuration requirements, verification collaterals, etc. Work with verification teams on assertions, test plans, debug, coverage, etc. Qualifications and Preferred Skills: 8+ years and current hands-on experience in microarchitecture and RTL development . Proficiency in Verilog, System Verilog . Familiarity with industry-standard EDA tools and methodologies . Experience with large high-speed, pipelined, stateful designs, and low power designs . In-depth understanding of on-chip interconnects and NoCs (Networks-on-Chip) . Experience within Arm ACE/CHI or similar coherency protocols. Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects, and NoCs. Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus. Experience with modern programming languages like Python is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. QUALIFICATION: BS, MS in Electrical Engineering, Computer Engineering, or Computer Science.

You will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Additionally, you will participate in defining the architecture and microarchitecture features of the block being designed. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals, as well as design integrity for physical implementation. It will be your responsibility to review the verification plan and implementation to ensure design features are verified correctly. You will also resolve and implement corrective measures for failing RTL tests to ensure the correctness of features. Providing support to SoC customers to ensure high-quality integration and verification of the IP block will also be a part of your role. Furthermore, you will drive quality assurance compliance for a smooth IP SoC handoff. Qualifications: - A Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience, or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience. - Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components. - Knowledge of power management is preferred, and experience with formal apps would be beneficial. - Expertise in Verilog and System Verilog-based logic design. - Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must. - Knowledge of considerations for performance, power, and cost optimization is desirable. - Knowledge of formal property verification using Jasper is preferred. - Demonstrate excellent self-motivation, communication, strong problem-solving, and teamwork skills. - Ability to set aggressive goals and meet/beat commitments. - Flexible enough to work in a dynamic environment and multitask seamlessly, with the ability to work independently and in a team. - Knowledge in IPs like I2C, I3C, SPI, UART, etc., is preferred. - Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage. In this role, you will work within the Client Computing Group (CCG) at Intel, responsible for driving business strategy and product development for Intel's PC products and platforms. The CCG aims to deliver purposeful computing experiences that unlock people's potential, allowing each person to focus, create, and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. This role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site. Please note that job posting details such as work model, location, or time type are subject to change. ,

You will be part of a highly skilled and challenging high-speed parallel PHY design team, focusing on DDR, LPDDR, and other similar interfaces. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as data paths, analog calibration, training, IP initialization, low power control, test, and loopback. You will be involved in various aspects of design and verification from specification to silicon, including interface design for controllers and SoCs. Actively participate in problem-solving and implementing improvements, as well as mentoring and coaching other design team members on technical issues. Collaborate with Analog designers to ensure seamless interface between Digital and Analog circuits. You should possess a strong fundamental knowledge of digital design, Verilog, and scripting languages. Experience with micro-architecture, Asynchronous digital designs, Synthesis, STA, Lint & CDC, DDR/LPDDR JEDEC protocol, DDR PHY designs, training algorithms, data path designs, domain transfer designs, APB/JTAG, and DFI is required. A degree in M.S./M.Tech, BS/BE (Electronics) and a minimum of 7 years of experience are necessary for this role. Micron Technology is a global leader in memory and storage solutions, driving the transformation of information into intelligence. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers a wide range of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The innovations created by Micron's team enable advances in artificial intelligence and 5G applications, powering opportunities from data centers to the intelligent edge and enhancing the client and mobile user experience. For more information, please visit micron.com/careers. For assistance with the application process or requests for reasonable accommodations, please contact hrsupport_in@micron.com. Micron is committed to prohibiting the use of child labor and complying with all relevant laws, rules, regulations, and international labor standards.,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

As an experienced professional in ASIC development with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, you will be leading a team of engineers in Bengaluru to deliver AI/ML compute intensive IPs and subsystems. With 8 years of experience in Verilog/SystemVerilog, VHDL, or Chisel, and 4 years of people management expertise, you will collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Your responsibilities will include taking ownership of complex IPs or subsystems, implementing RTL, and driving design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Additionally, you will be tasked with identifying and driving power, performance, and area improvements for the domains owned. Your role will involve working on cutting-edge SoCs used to accelerate machine learning computation in data centers. You will be solving technical issues with innovative micro-architecture and practical logic solutions, and evaluating design options with complexity, performance, power, and area in mind. Furthermore, you will contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The future of AI/ML hardware acceleration awaits you in this role, where you will have the opportunity to shape cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your contributions will play a crucial role in delivering high-quality designs for next-generation data center accelerators, collaborating with various teams such as architecture, verification, power and performance, and physical design. The Technical Infrastructure team at Google is responsible for the architecture that keeps everything running smoothly online. From data centers to the next generation of Google platforms, this team ensures Google's product portfolio remains at the forefront of innovation. By joining this team, you will play a key role in maintaining networks, ensuring users have the best and fastest experience possible.,

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. Your role will involve RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking applications. You will be creating block-level micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance throughout the design flow. In addition to your technical responsibilities, you will also need to work and communicate effectively with multi-site teams. Your experience in ASIC product life cycle, including requirements, design, implementation, test, and post-silicon validation, will be essential in this role. If you are passionate about technology solutions and enjoy working in a collaborative environment, we encourage you to apply for this position. Join us at MarvyLogic and be a part of building futuristic and impactful solutions that make a difference in various industries. Your experience with emerging technologies and your contributions to our team may help you evolve both professionally and personally, leading to a more fulfilling life.,

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System Verilog, UVM-based environments, AXI3/4/5, and preferably PCIe. Previous experience in RTL design of complex protocols and IP development teams is highly advantageous. As a member of the Cadence High-Speed SerDes PHY IP Front end Design team, you will be responsible for defining microarchitecture, leading ASIC design, collaborating with cross-functional teams, mentoring junior members, and fostering a high-performance team culture. Requirements for this role include a Bachelor's degree in Electronics Engineering with at least 7 years of experience, a Master's degree with 5 years, or a Ph.D. with 2 years in Digital Design. You should have hands-on experience in micro-architecting digital blocks, RTL implementation in Verilog/SV, SDC definition, STA, Lint Checks, CDC, and Synthesis. Knowledge of protocols such as Ethernet, USB, PCIe, MIPI(DPHY), and HDMI/Display is desired, along with the ability to work closely with Analog design teams and develop high-speed critical digital circuits and signal processing blocks.,

Responsibilities: In this role, he/she would be the technical lead responsible for driving design, quality and debug throughput of top-level development and support post-silicon debugs. Working with architects and verification leads and driving quality microarchitecture specifications. Developing design infrastructure and needed improvements Developing design strategy for quality. Driving design closure to meet schedule with quality Working with each domain (sub-system) lead and guide them to get better quality and design outcome. Helping management with risk assessment on features, quality, and schedules Working with sub-system design leads to identify potential areas of formal verification. Requirements: BS +14 years or MS +12 years work experience preferred. Should have end to end GFX/Compute design experience and system knowledge. Experience with advanced design methodologies and microarchitecture. Familiarity with all verification areas and tools and confirmed understanding of verification/technology interactions Good understanding of memory hierarchy, caches, address translations schemes. Good understanding of general dram technologies and address translation schemes Familiarity with GFX pipeline and GPU design is plus Familiarity with Computer organization/architecture. Strong analytical/problem solving skills and pronounced attention to details. Formal property-based verification knowledge is an added plus. Must be a self-starter, and able to independently drive tasks to completion. Good teamwork and communications skills are required Academic credentials: B.E/B.Tech or M.E/M.Tech degree in ECE / Electrical Engineering / Computer Engineering

The job is located in Bangalore and requires 3-5 years of experience for 2 available positions. The primary responsibility involves RTL Design, with a focus on practical experience in RTL development using VHDL and/or Verilog. This includes functional and structural RTL design, design partitioning, simulation, regression, and collaboration with design verification teams. The ideal candidate should be familiar with the latest RTL languages and tools such as Modelsim, VCS, Design Compile, Prime Time, Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, among others. Desirable experience includes strong processor architecture knowledge, microarchitecture implementation, microprocessor integration, and low power design. Effective communication skills, teamwork abilities, self-direction, and time management skills are essential for this role. Preferred qualifications include developing RTL for multiple logic blocks of a DSP core, running various frontend tools for linting, clock domain crossing, and synthesis, collaborating with the physical design team on design constraints and timing closure, working with the power team on power optimization, and collaborating with the verification team on test plan, coverage plan, and coverage closure. The educational requirement for this position is a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field.,

You will be part of a highly skilled and challenging high-speed parallel PHY design team, working on DDR, LPDDR, and other similar projects. Your responsibilities will include designing and developing high-speed interface PHY and its sub-blocks, such as high-speed data paths, analog calibration, training, IP initialization, low power control, test, and loopback functionalities. You will be accountable for various aspects of design and verification starting from specification to silicon, along with interface design for controllers and SoCs. Your active involvement in problem-solving and identifying opportunities for improvement will be crucial. Additionally, you will be mentoring and coaching other design team members on technical issues, collaborating closely with Analog designers to ensure a seamless interface between Digital and Analog circuits. Your skill set should include strong fundamental knowledge of digital design, Verilog, and scripting languages. Experience with micro-architecture and Asynchronous digital designs is required. Working knowledge of Synthesis, STA, Lint & CDC, DDR/LPDDR JEDEC protocol, DDR PHY designs, training algorithms, data path designs, domain transfer designs, APB/JTAG, and DFI is essential. The ideal candidate should have an M.S./M.Tech or BS/BE degree in Electronics. Micron Technology is a global leader in innovating memory and storage solutions, with a vision to transform how the world uses information to enrich lives. Micron's relentless focus on customers, technology leadership, and manufacturing excellence delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through the Micron and Crucial brands. Micron's innovations power the data economy, enabling advances in artificial intelligence and 5G applications from data centers to the intelligent edge, and across client and mobile user experiences. For more information about Micron Technology, Inc. and career opportunities, please visit micron.com/careers. To seek assistance with the application process or request reasonable accommodations, please reach out to hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all applicable laws, regulations, and international labor standards.,

You should have at least 8 years of experience in Micro-architecture, SoC development, and full-chip design for multi-million gate SoCs. Your expertise should include a strong understanding of the design convergence cycle, encompassing architecture, micro-architecture, Verification, Synthesis, and timing closure. You should also be adept at managing IP dependencies and planning front-end design tasks effectively. Additionally, you should have experience in designing and developing high-speed serial IO protocols. Your skills should cover the implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, and low power modes. Experience in CPU, bus fabrics, or coherence/noncoherent NOC domains would be highly desirable for this role.,

You are invited to join Lattice Semiconductor as a SoC RTL Design Engineer in Pune, India. Lattice is a global community of engineers, designers, and specialists working in collaboration with sales, marketing, and support teams to develop cutting-edge programmable logic solutions that are revolutionizing the industry. As a SoC RTL Design Engineer at Lattice Semiconductor, you will be part of a dynamic team dedicated to IP design and full chip integration. This role offers ample opportunities to contribute, learn, innovate, and grow within a fast-paced and results-oriented environment. Key responsibilities of this role include working on FPGA projects, RTL design, SoC integration, and ensuring design quality through various quality checks. You will collaborate with architects and micro-architects to define design specifications and drive logic design efforts for key FPGA blocks and full chips. To excel in this role, you will need a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent, along with at least 5 years of experience in logic design across multiple silicon projects. Expertise in SoC integration, familiarity with FPGA designs, and the ability to work with various teams across different sites and time zones are essential for success in this position. At Lattice, we value our employees as our greatest asset and are committed to providing a comprehensive compensation and benefits program to attract, retain, and celebrate top talent in the industry. If you thrive in a collaborative environment, are a problem-solver, and have a passion for innovation, Lattice Semiconductor may be the perfect fit for you. Join us at Lattice Semiconductor and be part of a team that is dedicated to customer success and driven by a shared commitment to excellence. To learn more about our innovative programmable design solutions, visit www.latticesemi.com and follow us on Twitter, Facebook, and RSS. At Lattice, we embrace diversity and welcome applications from all qualified candidates who can contribute to our dynamic workplace. Feel the energy at Lattice Semiconductor and discover a rewarding career where you can make a real impact in the industry.,

You will be joining Qualcomm India Private Limited as a Sub-System Hardware Architect specializing in ASIC design for AI within the Engineering Group > Hardware Engineering. Your primary responsibility will be to define and lead the hardware architecture for ASIC components within the Turing subsystem, ensuring they meet performance, reliability, power, and scalability requirements. You should have proven experience in designing ASIC sub-system hardware components for AI applications, strong knowledge of ASIC design tools and methodologies, and excellent problem-solving skills. Your role will involve collaborating with cross-functional teams to define hardware requirements, developing and implementing ASIC hardware architecture strategies for AI, conducting power assessment, and writing detailed hardware specifications. To qualify for this role, you should have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 8 to 12 years of experience in ASIC design and architecture. Additionally, you should possess expertise in micro-architecture, RTL coding, clock controller design, low power designs, and have excellent communication skills. You will be expected to provide technical guidance and mentorship to junior engineers, stay updated with the latest advancements in ASIC technology and AI applications, and ensure compliance with company policies and procedures. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require accommodations, you can contact Qualcomm at disability-accommodations@qualcomm.com. Please note that this email address is specifically for disability accommodations and not for updates on applications or resume inquiries.,

As an experienced VLSI SoC RTL designer with 10 to 15 years of work experience, you will play a crucial role in securing an optimal digital IP and circuit. Your responsibilities will include designing and verifying functions in alignment with the required goals. You will have the opportunity to contribute to various areas such as SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, and Flash Subsystem based on your skills and interests. To excel in this role, you should have a strong understanding of digital design principles, with specific knowledge of AMBA SoC BUS protocols like APB, AXI, and AHB. Your tasks will involve creating micro-architecture and detailed design documents for SoC design while considering performance, power, and area requirements. Proficiency in debugging and experience with DV tools such as Verdi and NCSIM will be essential. Preferred candidates will have SOC integration experience at the Top Level, Block Level, or Subsystem level. Collaboration with the DV team to enhance verification coverage and working on GLS closure with DV, PD, and Modelling team will be part of your responsibilities. Knowledge of clock domain crossing (CDC), Linting, UPF, ASIC Synthesis, static timing reports analysis, and formal checking is required. Furthermore, you will be involved in defining constraints and ensuring critical high-speed path timing closure in collaboration with back-end teams. If you are seeking a challenging opportunity to leverage your VLSI SoC RTL design skills and contribute to cutting-edge projects, this role offers a stimulating environment to grow and excel.,

You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC project, expertise in IP design, subsystem design, SoC integration, and successful leadership of a team to deliver projects on time. If you are interested in this position, please share your updated CV with gayatri.kushe@tessolve.com or connect on 6361542656.,

As a Senior ASIC RTL Design Engineer at Google, you will be a key member of a team dedicated to creating custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions globally. Your expertise will play a crucial part in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As part of the Devices & Services team, you will have the opportunity to combine the best of Google AI, Software, and Hardware to create innovative and helpful user experiences. You will be involved in researching, designing, and developing new technologies and hardware to enhance user interactions with computing, making them faster, seamless, and more powerful. **Responsibilities:** - Lead a team to deliver fabric interconnect design for ASICs. - Develop and enhance RTL design to meet power, performance, area, and timing objectives. - Define key details such as interface protocols, block diagrams, data flow, and pipelines. - Oversee RTL development and debug functional/performance simulations. - Collaborate effectively with multi-disciplined and multi-site teams. **Minimum Qualifications:** - Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. - 15 years of experience in ASIC RTL design. - Proficiency in RTL design using Verilog/System Verilog and microarchitecture. - Experience with ARM-based SoCs, interconnects, and ASIC methodology. **Preferred Qualifications:** - Master's degree in Electrical Engineering or Computer Engineering. - Proven experience in driving multi-generational roadmap for IP development. - Experience in leading interconnect IP design teams for low power SoCs.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. You should possess at least 5 years of experience in ASIC development with Verilog/SystemVerilog and VHDL. It is essential to have experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Additionally, experience in micro-architecture and design of subsystems is required. Preferred qualifications: Ideally, you should have experience in SoC designs and integration flows. Proficiency in scripting languages such as Python or Perl would be beneficial. Knowledge of high performance and low power design techniques is preferred, along with an understanding of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the job: As a member of our team, you will contribute to shaping the future of AI/ML hardware acceleration, focusing on cutting-edge TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Your responsibilities will involve verifying complex digital designs, specifically related to TPU architecture and its integration within AI/ML-driven systems. You will work on ASICs used to enhance data center traffic, collaborating with various teams to deliver high-quality designs for next-generation data center accelerators. Innovation, problem-solving, and evaluation of design options will be key aspects of your role, with a focus on micro-architecture and logic solutions. The ML, Systems, & Cloud AI (MSCA) organization at Google is responsible for designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. Prioritizing security, efficiency, and reliability, the team works towards shaping the future of hyperscale computing, impacting users worldwide. Responsibilities: - Own microarchitecture and implementation of subsystems in the data center domain. - Collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. - Perform Quality check flows like Lint, CDC, RDC, VCLP. - Drive design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and implement power, performance, and area improvements for the domains owned.,

As a member of Micron Technology's innovative memory and storage solutions team, you will be part of a dynamic group dedicated to transforming information into intelligence, inspiring advancements in learning and communication. Specifically, you will contribute your expertise to a high-speed parallel PHY design team, focusing on DDR, LPDDR, and other related technologies. Your responsibilities will include designing and developing high-speed interface PHY components, such as data paths, analog calibration, training algorithms, IP initialization, low power control, and more. You will play a crucial role in various aspects of design and verification, from specification to silicon implementation, collaborating on interface design for controllers and System on Chip (SoC) products. In this role, you will actively engage in problem-solving activities and identify opportunities for improvement. You will also have the opportunity to mentor and coach other team members on technical issues, ensuring a smooth interface between digital and analog circuits by working closely with Analog designers. To excel in this position, you should possess a strong foundation in digital design, Verilog, and scripting languages. Experience with micro-architecture, asynchronous digital designs, synthesis, Static Timing Analysis (STA), linting, Clock Domain Crossing (CDC), DDR/LPDDR JEDEC protocols, DDR PHY designs, training algorithms, data path designs, domain transfer designs, APB/JTAG, and DFI will be beneficial. Ideally, you hold a Master's or Bachelor's degree in Electronics. By joining Micron Technology, you will be part of a company that leads the industry in memory and storage solutions, driving innovation and enriching lives through technology. Micron's commitment to customer focus, technology leadership, and operational excellence ensures the delivery of high-performance products that empower advances in artificial intelligence, 5G applications, and more. For more information about Micron Technology, please visit micron.com/careers. If you require assistance during the application process or need reasonable accommodations, please reach out to hrsupport_india@micron.com. Micron Technology strictly prohibits the use of child labor and adheres to all applicable labor laws, regulations, and international standards.,

Qualcomm India Private Limited is seeking a skilled individual to join their Engineering Group in the Hardware Engineering department. As a part of the team, you will be responsible for defining the Debug Enabling Tools Strategy for the next generation CPU product line before design execution. This includes defining the DFD Hardware Validation Strategy, aligning with customers and architecture/micro-architecture teams, estimating efforts, identifying equipment and platform requirements, and ensuring the overall validation scope is met. You will also drive the DFD Domain by defining validation coverage metrics across all validation teams engaged from HW design through post-silicon and beyond. It will be your responsibility to identify coverage gaps between teams and address them by adding additional test cases to their respective plans. Additionally, you will serve as the customer voice for DFD Architecture/micro-Architecture owners, providing detailed feedback on DFD feature definition and implementation to meet customer requirements. To be considered for this role, you must have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, with at least 4 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience in the mentioned fields will also be considered. Qualcomm is an equal opportunity employer and is committed to providing an accessible application/hiring process for individuals with disabilities. If you require accommodations during the process, you may reach out to disability-accommodations@qualcomm.com or call Qualcomm's toll-free number provided on the website. Qualcomm expects all its employees to adhere to the company's policies and procedures, including security measures and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes on behalf of individuals, and any such submissions will be considered unsolicited. For more information about this role, please contact Qualcomm Careers directly.,

Key Responsibilities: Hands-on microarchitecture and RTL development for IP blocks Develop microarchitecture based on design specifications, including HW-SW interface definition IP-level verification and debugging for video and audio subsystems Work on MIPI CSI and DSI protocols understanding at protocol and implementation level Collaborate with design, verification, and software teams to ensure high-quality deliverables Drive or contribute to test plan creation, environment development, and coverage closure

Job Title: SoC Design lead/manager Expectation: 12+ Years of relevant industry experience in multiple SoC designs Strong technical background in driving SoC design independently Experience in processor system integration, NoC design and integration, Good understanding of high-speed protocols such as PCIe/DDR/HBM/Ethernet etc.. Strong experience with AXI/AHB bus protocols. Defining sign-off quality design constraints for SoC. Hands-on expertise with low-power design techniques such as UPF/CPF. Experience in Security aspects in SoC [secure JTAG, encryption/decryption] &secure boot design. Experience in Lint/CDC checks Hand-on experience in Verilog HDL, System Verilog, C/C++ Drive one or more teams for their respective deliverables. Ensure the quality of deliverables and take necessary steps to improve the quality Excellent analytical and problem-solving skills. Excellent communication skills to interact with cross-functional teams to build consensus. Good teamwork spirit and collaboration skills with team members. Education BTech or MTech or equivalent experience in Electronics Engineering.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.,

• Design Methodology, Micro-architecture, RTL. • Work with the architecture team to develop the uArch & Subsequently write RTL. • Develop Design Methodology, starting with the machine learning architecture. • Synthesis, STA, Equivalence checking. Required Candidate profile * EXP in SOC design methodology, Micro-architecture, Emulation & back-end DEV., & Chip Bring-up. * EXP in Developing ARM CPU based SoCs, Network-on-Chip & interfaces such as MIPI-CSI, Ethernet & PCIe