17 Microarchitecture Jobs

Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

As a Hardware Engineer at IBM , you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market. Your Role and Responsibilities As a Logic Design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet secure, high-performance & low-power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL. Additional responsibilities: Logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements : Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required Education Bachelor's Degree Preferred Education Master's Degree Required Technical and Professional Expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures . Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache, Mem, IO). Understand RISC V core . Experience with VLSI Design in VHDL / Verilog .

As a Hardware Engineer at IBM , you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market. Your Role and Responsibilities As a Logic Design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet secure, high-performance & low-power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL. Additional responsibilities: Logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements : Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required Education Bachelor's Degree Preferred Education Master's Degree Required Technical and Professional Expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures . Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache, Mem, IO). Understand RISC V core . Experience with VLSI Design in VHDL / Verilog .

As a CPU Processor Verification Engineer , you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market. Your role and responsibilities Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

As a CPU Processor Verification Engineer , you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market. Your Role and Responsibilities Lead the unit-level pre-silicon functional & performance verification of the front end of the pipeline for our next-generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction Fetch, Branch Prediction, and Instruction Decode units of the high-performance processor CPU. Develop verification test plans for both functional and performance verification, including the estimation for coverage closure. Support higher-level core/system simulation environments. Participate in post-silicon lab bring-up and validation of the Hardware. Lead, guide, and mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively communicate progress, potential challenges encountered, and milestones achi

As a CPU Processor Verification Engineer , you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market. Your Role and Responsibilities Lead the unit-level pre-silicon functional & performance verification of the front end of the pipeline for our next-generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction Fetch, Branch Prediction, and Instruction Decode units of the high-performance processor CPU. Develop verification test plans for both functional and performance verification, including the estimation for coverage closure. Support higher-level core/system simulation environments. Participate in post-silicon lab bring-up and validation of the Hardware. Lead, guide, and mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively communicate progress, potential challenges encountered, and milestones achi

We are seeking a skilled Back End Developer with a focus on NodeJS to join our dynamic team. As a Back End Developer, you will be responsible for developing server-side logic, database integration, and ensuring high performance and responsiveness to requests from the front-end. We Eximietas Design About Eximietas History Careers Job Openings Connect Contact Us Engineer Silicon Silicon Design MicroArchitecture and RTL design Design Verification Physical Implementation Analog/Mixed Signal DFT Verification & Validation Presilicon Validation Post Silicon Validation Devices Embedded Software Firmware BSP & Drivers Multimedia Connectivity Edge AI Hardware Design Services High Speed Digital Design Hardware & Board Design Services Cloud & Digital Infrastructure & DevOps Secure Foundation Infrastructure as Code CI/CD Monitoring & Observability Modernization & Migration Workload Migration Application Development API & Application Integration Application Migration Modernize Applications Database Modernization Enterprise Database Migration Cyber Security Security Strategy & Compliance Identity & Access Management Infrastructure & Application Security Data Security & Privacy Threat Intelligence AI & Data Analytics AI & Machine Learning MLOps Conversational AI Generative AI Data Analytics Data Warehouse & Lake Modernization Business Intelligence & Data Visualization Excellence Why Eximietas Case Studies Blogs The Think Tank News and Events Click We Eximietas Design About Eximietas History Careers Job Openings Connect Contact Us Engineer Silicon Silicon Design MicroArchitecture and RTL design Design Verification Physical Implementation Analog/Mixed Signal DFT Verification & Validation Presilicon Validation Post Silicon Validation Devices Embedded Software Firmware BSP & Drivers Multimedia Connectivity Edge AI Hardware Design Services High Speed Digital Design Hardware & Board Design Services Cloud & Digital Infrastructure & DevOps Secure Foundation Infrastructure as Code CI/CD Monitoring & Observability Modernization & Migration Workload Migration Application Development API & Application Integration Application Migration Modernize Applications Database Modernization Enterprise Database Migration Cyber Security Security Strategy & Compliance Identity & Access Management Infrastructure & Application Security Data Security & Privacy Threat Intelligence AI & Data Analytics AI & Machine Learning MLOps Conversational AI Generative AI Data Analytics Data Warehouse & Lake Modernization Business Intelligence & Data Visualization Excellence Why Eximietas Case Studies Blogs The Think Tank News and Events Click Cloud / 3+ Years Back End Developer Bengaluru/Bhubaneswar Job Description We are seeking a skilled Back End Developer with a focus on NodeJS to join ourdynamic team. As a Back End Developer, you will be responsible for developing server-side logic, database integration, and ensuring high performance and responsiveness to requests from the front-end. You will collaborate with cross-functional teams to define, design, and ship new features and enhancements to our existing applications. The ideal candidate will have a strong understanding of Backend technologies, excellent problem-solving skills, and a passion for creating scalable and efficient systems. Responsibilities Design, develop, and maintain scalable, high-availability backend services using js. Develop RESTful APIs using js and Express to ensure seamless communication between the frontend and backend components. Integrate and manage databases, both relational (e.g., PostgreSQL) and/or NoSQL (e.g., MongoDB), to store, retrieve, and manipulate data Write clean, maintainable, and efficient code; perform code reviews to ensure code Implement thorough testing practices, including unit and integration testing, to maintain code quality and Requirements Bachelor s degree in computer science, Software Engineering, or a related 3+ years of professional experience as a Backend Developer, specializing in Strong command over js and Express for backend development. Solid experience with both SQL (e.g., PostgreSQL) and/or NoSQL (e.g., MongoDB) Familiarity with version control systems (e.g., Git) and agile development Excellent problem-solving skills and the ability to debug and troubleshoot complex technical Strong communication skills, both written and verbal, to collaborate effectively with technical and non-technical Strong experience with microservices architecture and system design. Preferred Qualifications Experience with cloud platforms such as AWS, Azure, or Google Cloud Knowledge of containerization technologies like Docker and orchestration tools such as Familiarity with continuous integration and continuous deployment (CI/CD) Understanding of Agile methodologies and DevOps

Greetings from Wafer Space! Exciting Opportunity for Senior RTL Design Lead Engineers Automotive SoC Domain Job Title: Senior RTL Design Engineer No. of Positions: 4 Notice Period: Immediate to 30 Days Only Referrals: Please refer only suitable and relevant profiles About the Role: We are looking for experienced RTL Design Engineers to join our team developing next-generation solutions for automotive camera and display systems. This is a key position requiring strong technical expertise in microarchitecture and RTL coding, with an emphasis on high-performance, low-power ASIC designs. Key Responsibilities: Define microarchitecture and implement RTL to meet performance, power, and area (PPA) goals. Collaborate with software teams to define hardware/software interfaces, configuration requirements, and verification collaterals. Partner with verification teams on assertion development, test plans, debugging, and coverage closure. Ensure adherence to industry-standard ASIC design methodologies. Drive design quality and functional safety for automotive-grade solutions. Required Skills & Qualifications: Bachelors/Masters/Ph.D. in Electrical/Electronics Engineering. 5–10 years of hands-on experience in RTL design and microarchitecture development. Strong proficiency in Verilog and SystemVerilog. Proven experience in designing IP blocks for video/audio pipelines. Sound understanding of MIPI CSI and DSI protocols. Experience with high-speed, pipelined, and low-power designs. Familiarity with EDA tools and design methodologies (e.g., Synopsys, Cadence). Experience working on designs complying with automotive functional safety (ISO 26262) is a plus. Excellent problem-solving, communication, and team collaboration skills. Note: Only candidates with a notice period of 30 days or less will be considered. Please share or refer profiles that are strictly relevant to the requirements.

NES SOC Architecture team is looking for an outstanding engineer to work on definition of NEX SoC(s) for Intel Server, Client and IoT platforms. In this role, you will develop and drives end-to-end SoC architecture for highly optimized, modular, and scalable SoC, based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle.You will collaborate across disciplines to analyze workloads, identify opportunities for improvement, determine priorities, and balance trade-offs. Responsibilities include: Determining functional requirements based on product goals, use cases, and workload analysis. Defining SoC architecture to meet product requirement and deliver architecture specifications. Evaluates feasibility trade-offs and explores and defines new approaches and novel architectures for SoC. Invents, conceptualizes, and specifies microarchitecture and architectural features for next-generation products to deliver optimized SoC for multiple segments from high performance computing to extreme low-power products. A successful candidate will demonstrate. Broad knowledge of SoC architecture. Performance, power trade-off understanding. Deep expertise in domains such as reset, clock, coherency, debug, power management, performance evaluation Exceptional communication skills. Collaborates with design engineers, system engineers, verification engineers, structural design engineersto improve the overall design of SoC and overcome constraints. Work will include a combination of individual contribution and leveraging team participation through mentoring and leadership of technical initiatives. Qualifications: Minimum Qualifications: Bachelor's degree or higher in Computer Science or Electronics Engineering, 15+ years relevant experience in Silicon development in Arch/Uarch, Modeling, Designincluding multiple project development life cycles with at least one as lead architect or lead u-architect.

SENIOR LOGIC DESIGN ENGINEER Fortune 100 Organization Location: Bangalore Title Logic Design Engineer Your Role and Responsibilities As a Logic Design Engineer, you will play a pivotal role in the end-to-end development of features with significant impact on our Mainframe and/or Power customers. From conceptualization to validation, you will be responsible for developing features, presenting proposed architectures, estimating efforts, and collaborating across various teams to ensure successful implementation. Your primary responsibilities include: Feature Development and Architecture: Develop features and propose architectures in high-level design discussions, ensuring alignment with project goals and customer requirements. Effort Estimation: Estimate the overall effort required for feature development, providing valuable input to project planning and scheduling. Cross-Functional Collaboration: Collaborate with verification, physical design, test generation, and mill code teams to develop features, fostering cross-functional teamwork and synergy. Pre-Silicon Design Sign-off: Sign off on design during the pre-silicon phase, ensuring readiness for tape-out and fabrication. Post-Silicon Validation: Validate hardware functionality post-silicon, conducting thorough testing to ensure feature integrity and performance. Required Technical and Professional Expertise Microarchitecture and Logic Design: 7 to 12 years of experience in microarchitecture and logic design, demonstrating proficiency in designing complex digital systems. VLSI Design in VHDL/Verilog: Experience with VLSI design using hardware description languages such as VHDL or Verilog, enabling efficient implementation of digital logic. Processor Architecture Understanding: Good understanding of processor architectures, including RISC and CISC, facilitating the development of features tailored to specific processor requirements. Designer Simulations: Experience in developing and performing designer simulations, ensuring functionality and performance goals are met prior to silicon realization. Design Closure and Verification Coverage: Proven ability to drive design closure, including test plan reviews and verification coverage analysis, ensuring comprehensive validation of designs. Preferred Technical and Professional Experience Power-Efficient Logic Design: Experience in designing power-efficient logic, optimizing designs for low power consumption without sacrificing performance. Physical Design and Timing Constraints: Understanding of physical design concepts and timing constraints, facilitating seamless integration with physical implementation and timing closure processes. Python Scripting: Proficiency in Python scripting, enabling automation of design tasks and enhancing productivity in design workflows. Preferred Education Master's Degree Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

General Summary: Bachelors /Masters degree in Engineering Relevant experience of 2-12 yrs in any of the mentioned domain - Design/Verification/ Implementation Will be working on cutting-edge Wireless Technology (IEEE 802.11) team. Strong fundamentals in core areas:Microarchitecture, Computer Arithmetic, Circuit Design, Process Technology Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Design You will be responsible for developing HW blocks (IP design), conduct High/Mid/Low level Design review and delivery IP to Subsystem team for making complex SoCs. You will be a critical part of the WLAN subsystem, contribute to IP design, sign-off the core to the SOC design team. Strong communication skills to work with design teams worldwide Verification Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C As a design verification engineer you will work on developing IPs catering to upcoming Wifi standards like 802.11bn and beyond. You will have opportunity to contribute to the life cycle of the technology right from IP specification, till productization/customer deployments, leveraging your verification, pre and post silicon debug expertise. Implementation Candidate will be responsible for next generation WLAN hardmacro implementation Extensive experience in Synthesis (DC or Genus), Formal Verification (LEC / Formality), Conformal Low Power, PTPX, Primetime, Conformal ECO

Chip Lead (Sr Mgr/Director) Hyderabad A Hyderabad based SoC product design company is looking for a talented, energetic and diligent SoC Director for leading the development of a new generation of devices. Job Description: We are seeking an experienced professional to lead full chip design for multi-million gate SoCs in the area of HBM. Job responsibilities include: Driving the specification of the chip with architect and design leads eventually cascading into block specifications. Make PPA decisions for the chip. Defining multiple development checkpoints for IP/SoC Design/DV/PD Come up with overall project plan and cascaded schedule details for other teams Work with Analog/Digital IP teams to laydown integration details for the IPs. Drive the full chip floorplan / bump maps and provide area/floorplan targets to IP teams. Define the sign-off criteria for the device. Define the SoC verification plan items/scenarios to be covered. Assist/Review the micro architecture definition for digital blocks Define RTL Quality gate criteria for integration – Lint/CDC/ Drive the timing constraints/timing analysis/closure activities. Define the DFT targets for the chip and cascade that into activities needed on the DFT front. Work with PD enginers to get the physical design closure. Handle tapeout formalities Qualifications: Close to 15 years of solid experience in SoC design. A self starter. Candidate ready to define things where none exist. Ready for once in a lifetime project exposure, but ready to do heavy lifting for the effort. Proven ability to develop architecture and micro-architecture from specifications. Understanding of chip I/O design and packaging is advantageous. Experience in reviewing top-level test plans. Expertise in Synopsys Design Compiler for synthesis and formal verification. Strong working knowledge of timing closure processes. Experience with post-silicon bring-up and debugging. Familiarity with SoC integration challenges. Knowledge of design verification aspects is essential. Experience from SoC specification to GDS and commercialization is highly desired. Ability to make timely and effective decisions, even with incomplete information. Demonstrated expertise in specific technical areas, with significant experience in related fields. Provide direction, mentoring, and leadership to small to medium-sized teams. Strong communication and leadership skills are necessary for effective collaboration with program stakeholders. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

In your new role you will: Defining, designing, and implementing very complex logic blocks. Performing architecture analysis and feasibility for these complex blocks. Working with the SoC lead for full chip implementation from launch to production . Performing RTL design, synthesis and DFT strategy, clocking strategy, validation and verification support. Utilizing industry standards and proprietary tools and methodologies for design, chip integration and design for test. Supporting cross functional teams, including product and test engineering, chip integration, circuit design, verification and validation, in taking SoC into production. Participating in customer design reviews Participate in detailed planning and monitoring to deliver on time milestones. Mentor and develop junior engineers.

Responsibilities: Define microarchitecture and design/implement various innovative, analog/mixed-signal blocks Deliver detailed specifications & documentation Develop circuit schematics and work closely with layout designers to drive designs to completion (including physical verification and backend/reliability flows) Work with various teams (Architecture, Behavioral modeling, Logical Design, Physical Design, Firmware, Design Verification, Silicon Bring-up) to ensure successful cross-team engagement and high-quality execution Mentor and supervise junior engineers. Equal opportunity position with excellent pay package! Qualifications & Skills: Analog/Mixed Signal Circuit design experience with tape out experience in several of the following : Receiver, Transmitter, delay locked loop/phase locked loop/injection locked loop, phase interpolator, phase mixer, equalization circuits (CTLE/DFE/FFE), bandgap, regulator, oscillator, PLLs etc. Experience in fin-fet & on chip inductor design is a plus. Experience in DDR/LPDDR/GDDR is a plus. Good understanding of CMOS and VLSI technologies (device physics, layout effects, sub-micron effects and device reliability) Solid knowledge of industry-standard tools and practices for analog/mixed-signal and high-speed digital designs (Cadence design environment, HSPICE etc) Able to analyze and lead characterization data from lab and volume testing Able to build VerilogA/AMS behavioral models is a plus. Knowledge of ESD, LDMOS is a plus. 3-5 bullet points Education and Experience: PhD, M.S./M.Tech, BS/BE (Electronics)

Job Description Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure highquality integration of the CPU block. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market. Qualifications Candidate must possess a master's degree in Electronics or Computer Engineering with at least 8+ or more years of experience in related field. Preferred Qualifications:Experience in Processor verificationExperience with Specman/SV Language is plus Experience in verifying Power Mgmt, Cache controllers and memory features is plus Experience with Formal verification techniques is a plus Strong background in scripting - PERL/Python System hardware and software debug skills Understanding of software and/or hardware validation techniquesSolid understanding of system and processor architecture, and the interaction of computer hardware with software. Candidate should demonstrate excellent Self-motivation, communication, strong problem solving, excellent in cross-site communication and teamwork skills.

• Design Methodology, Micro-architecture, RTL. • Work with the architecture team to develop the uArch & Subsequently write RTL. • Develop Design Methodology, starting with the machine learning architecture. • Synthesis, STA, Equivalence checking. Required Candidate profile * EXP in SOC design methodology, Micro-architecture, Emulation & back-end DEV., & Chip Bring-up. * EXP in Developing ARM CPU based SoCs, Network-on-Chip & interfaces such as MIPI-CSI, Ethernet & PCIe

Exciting Career Opportunity for Senior Manager, Digital/RTL Design (ASIC) Location: Bangalore, India Experience: 12+ Years Work Mode: Hybrid (3 days from the office) Company: A Leading Japanese Semiconductor Manufacturing Company Are you a seasoned Digital ASIC Design professional ready to take on a leadership role? We are seeking a Senior Manager Digital ASIC Design to join one of the worlds top Japanese Semiconductor Manufacturing companies in Bangalore. This is a unique opportunity to work on cutting-edge ASIC designs in a dynamic and innovative environment. Please Note: This role is exclusively for ASIC design (not FPGA or IT-related digital design). Key Responsibilities: Digital Design Leadership: Oversee and manage the Digital Design team, including resource planning, methodology development, and staffing, to support device/silicon design requirements and deliver on program deadlines . Mixed-Signal IC Expertise: 12+ years of experience in Digital Design , with a strong focus on Mixed-Signal ICs , particularly Power Management ICs (PMICs) . Define Digital-Analog boundaries and outline the Digital design scope for Analog-intensive ICs . Design & Architecture: Define micro-architectures and sub-blocks to enable optimized Digital design , RTL design , and Gate-level netlist development. Manage Clock Domain Crossing (CDC) across multiple clock domains while ensuring glitch-free operation. Technical Collaboration: Lead and collaborate on Logic Synthesis , Formal Verification , Power Estimation , and Static Timing Analysis (STA) . Drive the development of OTP, MTP, Efuse read/write , controller design, data bus management, and DFT architecture/integration . If you are passionate about leading advanced Digital Design and driving innovation , we want to hear from you! Apply Now! Send your resume by clicking "Apply" and sharing your CV. Lets connect on LinkedIn: linkedin.com/in/heena-kausar-3a2b94a4 Tag your connections who might be interested! Join us and shape the future of semiconductor technology !