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RTL ASIC Design Engineer/Lead/Manager

8 - 12 years

0 Lacs

karnataka

Posted:2 days ago| Platform: Shine logo

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Skills Required

microarchitecture verilog coding i2c spi uart apb ahb axi cdc leadership rtl asic front end design mas development development of module feature addition medium complexity protocols amba bus protocols quality check flows linting ip design subsystem design soc integration

Work Mode

On-site

Job Type

Full Time

Job Description

As an RTL Engineer and Lead at Tessolve Semiconductors in Bangalore or Hyderabad, your role will involve RTL ASIC front end design with microarchitecture and Verilog coding. Your key responsibilities will include: - MAS development - RTL coding - Development of module and feature addition - Experience in medium complexity protocols - Familiarity with slow speed protocols like I2C, SPI, and UART - Knowledge of AMBA bus protocols (APB, AHB, AXI) - Experience in quality check flows such as linting and CDC For candidates with 8+ years of experience, the expectations will be higher, including: - Very strong RTL coding skills - Micro-architecture (uArch) development - Ownership and delivery of a sub-system or top level in a SoC project - Expertise in IP design, sub-system design, and SoC integration - Successful leadership of a team of engineers to deliver projects on time To apply for this position, kindly share your updated CV to gayatri.kushe@tessolve.com or connect on 6361542656. Join us at Tessolve Semiconductors and be a part of our innovative team driving semiconductor technology forward.,

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Tessolve

Semiconductor and Electronics Engineering

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