7 Subsystem Design Jobs

As an RTL Engineer and Lead at Tessolve Semiconductors in Bangalore or Hyderabad, your role will involve RTL ASIC front end design with microarchitecture and Verilog coding. Your key responsibilities will include: - MAS development - RTL coding - Development of module and feature addition - Experience in medium complexity protocols - Familiarity with slow speed protocols like I2C, SPI, and UART - Knowledge of AMBA bus protocols (APB, AHB, AXI) - Experience in quality check flows such as linting and CDC For candidates with 8+ years of experience, the expectations will be higher, including: - Very strong RTL coding skills - Micro-architecture (uArch) development - Ownership and delivery of a s...

Position Title Embedded System Engineer Purpose of the Position Knowledgeable & experience person for Embedded system design considering overall system requirements. Function Electronics Design Department Engineering Location -Mahalunge, Pune Reporting To- Head Engineering PRIMARY RESPONSIBILITIES Key Accountabilities Responsibilities 1 Software Architecture Development & Requirement finalisation. Responsible to finalize overall System Architecture & system requirements for various projects based on scope of work & customer requirement. 2 Electronics Design a. Subsystem Design considering stringent Military Standards. b. Electronic card development using ORCAD 16.6 & Proteus. c. ARM Cortex /...

As an Individual Contributor in the IP / SS domain, your role involves driving roadmaps for the complete IP portfolio, focusing on logic design and architecting Complex IPs / Subsystems solutions. You will collaborate with a team of global experts to address design challenges and work on a wide spectrum of skills from high-level specifications to actual design implementation. **Key Responsibilities:** - Own and drive Roadmaps for complete IP / Subsystem domains portfolio within the global R&D team. - Perform benchmarks against industry players to ensure innovative features for customers. - Architect and Design complex IP and Subsystems for Automotive Self Driving Vehicles (ADAS), In-Vehicle ...

You should have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include designing and developing CXL and DRAM controller (DDR4/5) based intellectual property, engaging with other architects within the IP level to drive the Micro-Architectural definition, delivering quality micro-architectural level documentation, producing quality RTL on schedule by meeting PPA goals, being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. You will collaborate with the verification team to ensure implementation meets architectural intent, run quality checks such as Lint, CDC, and ...

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team in Bangalore/Hyderabad, India, contributing to cutting-edge technological work in the field of integrated circuits. Your expertise will be crucial in driving the design and verification efforts for complex IP/Subsystem/SoC blocks. Design Lead: In the role of RTL Design Lead, you will be responsible for ensuring bug-free RTL from requirements or specifications. Your experience in multiple tape-outs and driving the design effort for complex blocks will be instrumental in the success of our projects. Verification Lead: As a Verification Lead, your role will involve catching bugs and ...

You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC projec...

Within a tender or a project, reporting hierarchically to the EDU Brake&Air Mgr, and functionally to the Train System Engineer, undertaking a subsystem (brake, air production)from the requirements analysis to the validation and the reliability growth. translation of thecustomer and internal requirements in to design Writing Technical purchase specification of the subsystem interact closely with the suppliers, sourcing, industrialization, quality. leadinginternally and externally all interfaces topics - mechanical, electrical, pneumatic, communication. approve pneumatic scheme , electrical scheme for his perimeter. supervise the subsystem validation at supplier level, as well as the validatio...