3 Subsystem Design Jobs

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team in Bangalore/Hyderabad, India, contributing to cutting-edge technological work in the field of integrated circuits. Your expertise will be crucial in driving the design and verification efforts for complex IP/Subsystem/SoC blocks. Design Lead: In the role of RTL Design Lead, you will be responsible for ensuring bug-free RTL from requirements or specifications. Your experience in multiple tape-outs and driving the design effort for complex blocks will be instrumental in the success of our projects. Verification Lead: As a Verification Lead, your role will involve catching bugs and ensuring that the design intent is met. Your expertise in leading multiple tape-outs and closing the verification of complex blocks will be essential in delivering high-quality results. For the Design role, we are looking for a Senior RTL Subsystems Designer Lead with a minimum of 8 years of experience. You should be able to drive the Subsystem life cycle from requirements to final release phases, work on defining micro-architectures, coding RTL with best practices, and collaborate with cross-functional teams to drive projects to completion. Key skills required for the Design role include proficiency with standard protocols such as PCIe, DDR, UFS, USB, AMBA, hands-on experience with low power design, understanding of DFT requirements and architecture, and the ability to work effectively with cross-functional teams. For the Verification role, we are seeking a Senior Verification Lead with a minimum of 8 years of experience. You should be able to drive the complete Verification cycle, including crafting test plans, architecting verification environments, developing test infrastructure, and driving closure with coverage. Key skills required for the Verification role include proficiency with Functional Verification of standard protocols such as PCIe, DDR, UFS, USB, AMBA, power-aware Verification with UPF, gate-level verification hands-on experience, and the ability to work effectively with cross-functional teams to drive projects to completion. If you are passionate about pushing the boundaries of technology and working on challenging projects in the SysMoore era, we invite you to join our dynamic team at Synopsys and contribute to the exciting world of integrated circuit design and verification.,

You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC project, expertise in IP design, subsystem design, SoC integration, and successful leadership of a team to deliver projects on time. If you are interested in this position, please share your updated CV with gayatri.kushe@tessolve.com or connect on 6361542656.,

Within a tender or a project, reporting hierarchically to the EDU Brake&Air Mgr, and functionally to the Train System Engineer, undertaking a subsystem (brake, air production)from the requirements analysis to the validation and the reliability growth. translation of thecustomer and internal requirements in to design Writing Technical purchase specification of the subsystem interact closely with the suppliers, sourcing, industrialization, quality. leadinginternally and externally all interfaces topics - mechanical, electrical, pneumatic, communication. approve pneumatic scheme , electrical scheme for his perimeter. supervise the subsystem validation at supplier level, as well as the validation of the subsystem on the train. solve reliability issues in revenue service Performing the transverse requirement allocations to the various subsystems in close collaboration with the relevant specialists, Performing requirement development, coming from reference and applicable documents from Metiers, Standards, Certification, Safety, Platform and Customer Defining the Train System architecture, operational modes and functionalities taking as input the external/internal requirements Performing train system FMECA in coordination with RAMS team Ensuring consistency and compatibility between all the sub-systems specifications, Writing sub-system specification and architecture description (RSAD2) in collaboration with the SSE/PU/TCE according to train level architecture. Fill the Entry connector to question the TSS catalog. For non catalog components, under TSS design authority: Writes the Technical Purchasing Specification (TPS0 - Short Specification) when needed. Writes the TPS1 for supplier consultation and manages technical contact (TPS2) until design has been frozen Drives technical relationships with suppliers with close management of QCD commitments (CbC), risks & validation (including Design Reviews with suppliers). Supporting TSE to define applicable train configuration Ensuring coordination between TSS/PU/Metier on interfaces, performances, technical issues resolution during detailed design phase. On TSE request, participating to technical meetings with customer in order to provide support. V&V activities: Responsible for: Defining and performing Train verification strategy in close collaboration with all Engineering metiers, Certification & Validation teams and TSS Team and Participating Units. Writing the train level test specifications Ensuring the train integration and tuning. During train revenue service: Technical open issues resolution on TSE request, from investigation to modification implementation and problem closure, QCD and reporting: Responsible for: Performing reporting at project level (to TSE, via KPI) and metier level (via weekly reports) Supporting TSE for implementation and update of Engineering risks mitigation plan, change order process and QCD optimisation Providing Return of experience to be implemented in Reference Solutions. Knowledge & Experience : General technical competencies More than 2 years in Railways engineering