21 Ip Design Jobs

Job description Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/ Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/ Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/ Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Job description Role & responsibilities Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Preferred candidate profile Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 5+ years of technical experience. Related technical experience should be in/with: Silicon Design and/or Validation/Verification. Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for Ethernet or PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB , I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.

Job description ISSP FPGA prototyping delivers Intel's core products, therefore you will have a unique opportunity to take part in major activities that affect the entire organization and the high-tech world.Our FPGA design verification team is in charge of validating infrastructure designs used to prototype cutting edge Intel client, devices and data centers chips.We are looking for great, highly motivated problem-solvers seeking to make significant contributions and impact on the projects they work on.In your role you will plan, design and execute scalable and robust verification environments, learn complex digital computers flows and simulate the behavior of the RTL design in purpose of debug and development using advanced verification methodologies. Qualifications Studying towards a B.Sc. or MSc in Computer Science / Electrical Engineering / Computers Engineeringsome experience with OOP (C++, Java...)some understanding of chip design frontend flow (design/validation/synthesis)any relevant chip design / verification experience is a big advantage

You are an experienced RTL/FPGA Design Engineer with a minimum of 3 - 7 years of experience in the VLSI domain. You hold a BE/B.Tech degree in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or a closely related field from a recognized university with a strong academic background. Your role will be based in Ahmedabad or Bangalore. In this role, you will be responsible for RTL programming using Verilog/System Verilog or VHDL, possessing knowledge of the complete FPGA Design Development flow. You should be proficient with FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will engage in functional verification using Verilog/System Verilog or VHDL, optimize RTL code to meet timings and on-chip resources, and support all phases of FPGA-based product development activities. System Architecture Design, testing, and troubleshooting of hardware will also be part of your responsibilities. To excel in this position, you must have experience with Verilog/SystemVerilog or VHDL for design and verification, along with a deep understanding of FPGA design flow/methodology, IP integration, and design collateral. You should be capable of developing small IP blocks from scratch and conducting basic functional verification. Familiarity with protocols like SPI, I2C, UART, and AXI, as well as knowledge of Altera Quartus II Tool, Questasim, Modelsim, Xilinx tools like ISE and Vivado, and Microsemi tools like Libero, are essential. Understanding of USB, Ethernet, and external memories such as DDR, QDR RAM, and QSPI-NOR based Flash is also required. In terms of personal competencies, you should be self-motivated to learn and contribute, able to work effectively with global teams, and willing to collaborate in a team-oriented environment. Prioritization and execution of tasks to achieve goals in a fast-paced environment, along with strong problem-solving skills, are valuable assets. Your passion for writing clean and neat code that aligns with coding guidelines will be highly appreciated. If you meet these qualifications and are excited about the opportunity to work in the VLSI domain as an RTL/FPGA Design Engineer, we encourage you to apply now.,

KEY RESPONSIBILITIES: Defines, plans and drives projects and program plans based on management and senior technical guidance Possesses a thorough knowledge of the principles of project management andcanapply them effectively on small to large size projects Has responsibility for projects or processes of significant technical importance and for results that cross engineering project areas Initiates significant changes to existing processes and methods to improve project and teamefficiency Creates and maintains project management artifacts such as schedule, resource and resource forecast, risk and issues logs Provides unique views of project status updates and facilitates cross development team dependencies and communications Identify action or mitigation plans for issues orrisksthat arise during the project lifecycle Collaborates with core teams and execution teams to identify areas that require special attention or escalations to identify corrective actions Collect, analyze, organize and publish work performance data via dashboards and recurring statusreports Detail oriented with strong analytical and debugging skills Engage with IP and SOC teams to drive closure to IP RTL deliverables PREFERRED EXPERIENCE: Detailed oriented, self-driven with a strong sense of pride and ownership. At least 15 years of experience focused on IP and/or SOC design, verification with successful completion of multiple ASICs that are in production Strong organizational, problem-solving, interpersonal, presentation, written and verbal communication skills Ability to build relationships and work effectively as a self-starter and as part of a team Proactively involve team members in planning, decision-making and execution efforts People management experience is desirable Excellent verbal and written communication skills to handle all levels of interaction, including executive level Horizontal leadership/Matrix management experience Technicalprogrammanagementandcustomerrelationshipmanagement Collaborate in problem solving and mitigating risks with Engineering, Program/Project Management, Business Units and Product Management - both internal and external Strong knowledge of productivity and project tools including Jira, Confluence, Microsoft Office Suite Preferably with GPU background ACADEMIC CREDENTIALS: Bachelors orMastersdegree in Computer/Electrical Engineering Formal project management education, PMP / Scrum Master

You will be responsible for designing and developing Debug IPs focusing on CoreSight IP design. Your role will involve ensuring that the Debug IPs meet the required specifications and performance standards. You will utilize your expertise in RTL design using Verilog and/or SystemVerilog for complex SoC development. Additionally, you will apply your knowledge of Arm-based designs and/or Arm System Architectures to develop and optimize IPs. Collaboration with cross-functional teams, SoC integration & Architecture teams is essential to ensure successful IP delivery within specified timelines. Implementing rigorous verification processes to ensure that the IPs meet all functional and performance requirements is a key aspect of the role. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design for complex SoC development using Verilog and/or SystemVerilog is required. A strong understanding of Arm-based designs and/or Arm System Architectures is essential. Proficiency in IP design, verification, and delivery, with a focus on Debug IPs, is also a key requirement. Excellent communication and collaboration skills are necessary to effectively work with cross-functional teams. Preferred skills for this role include experience with CoreSight based Debug IP design and strong problem-solving and analytical skills.,

ASIC RTL DESIGN ENGINEER (4 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 4 to 10 Years Openings: 6 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 4-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus

As a VLSI Design Engineer at Kinara, you will be part of a dynamic team focused on edge AI technology, pushing the boundaries of what's achievable in machine learning and artificial intelligence. You will contribute to the development of state-of-the-art AI processors and high-speed interconnects, ensuring unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. Your role will involve working on cutting-edge semiconductor projects, requiring a blend of technical expertise, problem-solving skills, and collaborative teamwork. Your responsibilities will include defining micro-architecture and creating detailed design specifications, developing RTL code based on system-level requirements using Verilog, VHDL, or SystemVerilog, implementing complex digital functions and algorithms in RTL, and executing comprehensive test plans to verify RTL designs. You will optimize designs for power, performance, and area constraints, conduct simulation and debugging activities to ensure design accuracy, collaborate with verification engineers to develop test benches and validate RTL against specifications, and apply your strong understanding of digital design principles and concepts. To excel in this role, you should possess proficiency in writing and debugging RTL code, experience with synthesis, static timing analysis, and linting tools, familiarity with scripting languages like Python, Perl, or TCL for automation, and expertise in processor subsystem design, interconnect design, or high-speed IO interface design. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 5+ years of experience in RTL design and verification, is required. Proven experience in digital logic design using Verilog, VHDL, or SystemVerilog, familiarity with simulation tools such as VCS, QuestaSim, or similar, and hands-on experience with RTL design tools like Synopsys Design Compiler and Cadence Genus is preferred. At Kinara, we offer an innovative environment where technology experts and mentors collaborate to tackle exciting challenges. We believe in sharing responsibilities and valuing diverse viewpoints. If you are passionate about making a difference in the field of edge AI technology, we invite you to join our team and contribute to creating a smarter, safer, and more enjoyable world. Your application is eagerly awaited as we look forward to reviewing your qualifications and experiences. Make your mark with us at Kinara!,

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Design engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Strong in digital design. Strong in Xilinx Vivado IP & IPI tools till bit-generation. Knowledge of VHDL/Verilog/System Verilog. Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up. Proficiency in Linux environment. Good communication skills. Basic Job Deliverable: RTL coding, IP design, Modify/update existing IP as per requirements. Qualification: Bachelors/Master’s in ECE TekWissen® Group is an equal opportunity employer supporting workforce diversity.

Qualcomm India Private Limited is looking for a skilled Program Manager to join their Engineering Services Group. As a Program Manager, you will be responsible for developing, defining, and executing plans of record, including schedules, budgets, resources, deliverables, and risks. Your role will involve monitoring and driving the program from initiation through delivery, interfacing with internal and external stakeholders across functions on technical matters as needed. You will also be accountable for monitoring budget/spending, on-time delivery, and achieving program milestones, as well as representing the program and driving alignment across stakeholders. Your key responsibilities will include establishing day-to-day operational objectives, organizing interdepartmental activities to ensure the completion of the program on schedule, managing change control and escalations, assessing program/initiative issues and areas of risks, and collaborating with various stakeholders to resolve problems. You will be expected to identify risks, clearly communicate goals and results, conduct team meetings, document issues, and keep the extended team informed of the status and health of IP development/delivery. Additionally, you will monitor and ensure product/program/project schedule compliance and interact with senior management and executives on respective functional areas. The ideal candidate should possess a Bachelor's degree in Electrical/Electronic Engineering, Computer Science, or a related field. You must have experience in complete IP lifecycle development, domain knowledge on IP design, deep technical expertise on various components like DLL, PLL, LDO, ADC, DAC, and sensor design, verification, and bring-up. It is essential that you have worked on RTL to GDS flow of digital IPs, and spec to GDS flow for analog and mixed signal IPs, along with complete ASIC lifecycle development. Moreover, you should have strong Microsoft tools skills (Excel, Powerpoint, Word, MPP, PowerBI), proven analytics skill in the VLSI domain, established interpersonal skills, the ability to communicate effectively at all levels, and the capability to synchronize and motivate engineering leads to attain common goals. While not mandatory, it would be advantageous to have domain knowledge of PDK components, IP quality assurance plan, quality control, test Chip design management, and experience with tools like MS_PowerBI, JIRA, and Confluence. A total of 10+ years of experience, with at least 4 years in program management, is desired. If you have a Master's degree in Engineering, Computer Science, or a related field, hold a PMP Certification, and have 7+ years of program management experience, you are encouraged to apply. Experience in a role requiring interaction with senior leadership, working in a large matrixed organization, and using program management tools such as dashboards and Gantt charts would be considered a plus. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Applicants are expected to comply with all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs directly at Qualcomm, and staffing and recruiting agencies are not authorized to use the site or submit profiles on behalf of candidates. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, please reach out to Qualcomm Careers.,

As a highly experienced Verification Engineer at our dynamic team, you will drive innovation in advanced verification methodologies for complex semiconductor designs. Your key responsibilities will include leading the deployment of verification tools, platforms, and strategies for complex IPs, driving simulation-based and hardware-assisted verification efforts, applying expertise in various verification technologies, developing and enhancing verification methodologies, collaborating cross-functionally with IP design and DV teams, and mentoring junior engineers to foster a culture of technical excellence. You should have 10+ years of experience in verification engineering for complex hardware systems, deep expertise in simulation and debug, hands-on experience with Static/Formal verification tools and methodologies, exposure to hardware-assisted verification environments, strong analytical and problem-solving skills, a degree in Electrical Engineering, Computer Engineering, or related field, familiarity with industry-standard verification languages, experience with scripting and automation, and a track record of technical leadership and cross-functional collaboration. Join our team at Synopsys and be part of an environment that values agility, courage, excellence, and trust. You will have the opportunity to work on cutting-edge technology and make a real impact.,

You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC project, expertise in IP design, subsystem design, SoC integration, and successful leadership of a team to deliver projects on time. If you are interested in this position, please share your updated CV with gayatri.kushe@tessolve.com or connect on 6361542656.,

Qualcomm India Private Limited is looking for a Program Manager to join the Engineering Services Group. As a Program Manager, you will be responsible for developing, defining, and executing plans of record, including schedules, budgets, resources, deliverables, and risks. You will monitor and drive the program from initiation through delivery, interacting with internal and external stakeholders across functions on technical matters as needed. Additionally, you will monitor budget/spending, on-time delivery, and achievement of program milestones, representing the program and driving alignment across stakeholders. Your responsibilities will include establishing day-to-day operational objectives, organizing interdepartmental activities to ensure the program is completed on schedule, managing change control and escalations, assessing program/initiative issues and areas of risks, and working with various stakeholders to resolve problems. You will also identify risks, communicate goals and results clearly, conduct team meetings, document issues, and keep the extended team informed of the status and health of IP development/delivery. Monitoring and ensuring product/program/project schedule compliance, interacting with senior management and executives on respective functional areas, and motivating engineering leads to attain common goals are also key aspects of this role. The minimum qualifications for this position include a Bachelor's degree in Electrical/Electronic Engineering, Computer Science, or a related field, along with at least 4+ years of Program Management or related work experience. You should have deep technical expertise in areas such as DLL, PLL, LDO, ADC, DAC, and sensor design, verification, and bring-up. Experience in complete ASIC lifecycle development, RTL to GDS flow of digital IPs, spec to GDS flow for analog and mixed signal IPs, and MSIP design and verification is essential. Strong Microsoft tools skills, proven analytics skill in the VLSI domain, and established interpersonal skills are also required. Preferred qualifications include a Master's degree in Engineering, Computer Science, or a related field, PMP Certification, and 7+ years of Program Management or related work experience. Experience working in a role requiring interaction with senior leadership, a large matrixed organization, and program management tools such as dashboards and Gantt charts is desired. If you have a disability and need accommodations during the application/hiring process, Qualcomm is committed to providing accessible support. Please email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number for assistance. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking a job at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For more information about this role, contact Qualcomm Careers.,

This is a verification-focused individual contributor's role within the DesignWare IP Verification R&D team at our Bangalore Design Center, India. As a part of this team, you will be responsible for implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores and executing Verification tasks for the IP cores. You will collaborate closely with the RTL design team and work alongside a global team of expert Verification Engineers. The domains you will be working on include USB, PCI Express, Ethernet, and AMBA. Your responsibilities in this role will encompass a variety of tasks such as Test planning, Test environment coding at both unit and system levels, Test case coding and debugging, FC coding and analysis, and achieving quality metric goals and regression management. To be considered for this position, you should have a BS/BE in EE with 7+ years of relevant experience or an MS with 6+ years of relevant experience in IP cores verification and/or SOC verification. You should possess experience in developing HVL-based test environments, creating and implementing test plans, and extracting verification metrics like functional coverage. Additionally, you must have proficiency in HVL coding for Verification and hands-on experience with industry-standard simulators such as VCS, NC, MTI, along with relevant debugging tools. Exposure to verification methodologies like UVM/VMM/OVM is essential, and familiarity with HDLs such as Verilog and scripting languages like Perl is highly desired. A basic understanding of functional & code coverage, exposure to IP design and verification processes including VIP development, and good written and oral communication skills are crucial for this role. You should also be able to demonstrate strong analysis, debugging, problem-solving skills, and be self-driven. Join our Silicon IP business, where we focus on integrating more capabilities into an SoC faster. Synopsys offers the world's broadest portfolio of silicon IP, pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors. We aim to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and bring differentiated products to market quickly with reduced risk. At Synopsys, we are at the forefront of innovations that reshape the way we live and work, including self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. Our advanced technologies for chip design and software security power these breakthroughs. If you are passionate about innovation, we look forward to meeting you.,

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name RTL Design Lead/uArch/Design Engineer Position type: Permanent Total Exp: 10-15 years HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: We're looking for a highly skilled RTL Design Lead to lead our digital design team. The successful candidate will be responsible for designing, developing, and verifying complex digital circuits using RTL design methodologies. The RTL Design Lead will work closely with cross-functional teams to ensure seamless integration of digital design blocks into larger systems. Key Responsibilities: 1. Lead a team of RTL designers to design, develop, and verify complex digital circuits. 2. Develop and maintain RTL design methodologies, standards, and best practices. 3. Collaborate with architects to define and implement digital architecture. 4. Work closely with verification teams to ensure seamless integration of digital design blocks. 5. Participate in design reviews, provide feedback, and ensure design quality. 6. Develop and manage project schedules, resource allocation, and budgets. 7. Mentor and train junior designers to improve team capabilities. Requirements: 1. Bachelor's/Master's degree in Electrical Engineering, Computer Science, or related field. 2. 10+ years of experience in RTL design, with at least 3 years in a RTL design/uArch leadership role. 3. Strong expertise in digital design principles, RTL design methodologies, and verification techniques. 4. Proficiency in HDLs (Verilog/SystemVerilog/VHDL), design tools (e.g., Synopsys, Cadence), and scripting languages (e.g., Perl, Python). 5. Excellent leadership, communication, and project management skills. 6. Strong problem-solving skills, with the ability to analyze complex design issues. Nice to Have: 1. Experience with ASIC/FPGA design flows. 2. Knowledge of computer architecture, microprocessors, and embedded systems. 3. Familiarity with industry-standard design methodologies (e.g., OVM, UVM). 4. Certification in RTL design or related field. AMD (Dont Share AMD Profiles) Preferred candidate profile

Key Responsibilities: Lead full-cycle Analog IP Development from circuit design to layout, AMS verification, and characterization. Hands-on experience in designing LDOs, Band Gap References, Current Generators, POR, ADC/DACs, PLLs, Oscillators, IOs, Temperature Sensors, SERDES, PHYs, High-Speed IOs, and more. Design & layout expertise in advanced CMOS and lower FINFET nodes. Strong grasp of design constraints, layout quality, and PPA trade-offs. Experience conceptualizing and implementing chip-level mixed signal simulations (testbenches, scripts, etc) Ownership of characterization and post-silicon validationAbility to lead teams and drive high-quality execution across subsystems

You have a keen eye for detail and can identify design/architecture pitfalls across clock/reset domain crossings . Your ability to synthesize designs and ensure RTL and gate equivalence through formality checks is unmatched. You are a collaborative team player, ready to integrate IPs in SoCs/Subsystems and create RTL designs that meet customer needs. If you are ready to leverage your expertise in a role that shapes the future of semiconductor design, Synopsys is the place for you. What You'll Be Doing: Perform RTL Quality Signoff Checks such as LINT, CDC, and RDC. Understand design/architecture and develop timing constraints for synthesis and timing . Run preliminary synthesis to ensure design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates . Integrate IPs in SoCs/Subsystems and create RTL design as per customer needs. Collaborate with cross-functional teams to deliver high-quality RTL designs. The Impact You Will Have: Ensure high-quality RTL Signoff for semiconductor designs. Contribute to the development of cutting-edge semiconductor technologies. Improve design efficiency and performance through effective timing constraints. Enhance the reliability and functionality of SoCs and subsystems. Support customer success by delivering tailored RTL designs. Drive innovation in RTL Design and Verification methodologies.

Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. Reporting metrics and driving improvements in Emulation IP. Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. Staying ahead of evolving standards, understanding future changes, specification errata, and driving this understanding into both the Emulation IP and Design IP teams. Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for IP product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You'll Need: 10+ years of relevant experience. Results-driven mindset. Exposure on advanced protocols like PCIe and DDR interfaces. Experience with Zebu in the context of technology and IP verification. Proven track record in IP product development, specifically emulation. Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment.

Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You'll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting.

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. We are seeking engineers with experience in system and SoC level automotive cybersecurity concepts and implementations and knowledge of the ISO21434 cyber security standards and process. This position will be a hands-on role in defining and contributing to the architecture for the current cyber security hardware development to meet ISO 21434 standards working with various stakeholders in the Systems/Security Architecture/IP & SoC design teams. Responsibilities shall include the following: Overall responsibility of automotive cybersecurity architecture of the Automotive SoCs. Work with Product Marketing, system/SW security architects and IP security architects to deliver the security architecture of the SoC which addresses the security use case at the System level. Overall responsibility of product auto cybersecurity technical concept, hardware security requirements, cybersecurity architecture specification, review of security requirements for applicable subsystems Perform TARA (Threat Analysis & Risk Assessment) Review and approve TARA at subsystem/IP level Review implementation and verification of cybersecurity vulnerability analysis for applicable subsystems Coordinate technical issues related to cybersecurity with all applicable subsystems, all SoC domains. Work with functional safety architect and ensure there are no conflicting requirements between safety and security. Work closely with SoC and IP design teams, 3rd party IP vendors to review the design implementations and ensure meeting the architecture goals. Maintain a strong knowledge of Automotive cybersecurity best practices. Influence internal stakeholders with actionable data to ensure gaps to expectations are closed in a timely fashion. Establish and maintain healthy relationships with influential/decision making on cyber security throughout the organization. Work in a highly matrixed environment. This role frequently requires working with others to fulfill job responsibilities without direct authority. Minimum Requirements: Bachelor's degree in Electrical or Electronics Engineering, Computer Science, or related field. 8+ years in roles on Systems Engineering / SoC Architecture / Security IP Architecture and design. Minimum 5+ years experience in architecture and design of Security IP/Cores or system level Security Architecture. Has knowledge of cyber security-based product development flow and validation. Experience with ISO 21434 Cyber security standards. Has led Cybersecurity implementation in SOC/Cores/IP. Hands-on experience with automotive Cybersecurity ISO 21434 standard spec and implementation. Structured problem-solving capability and ability to work with teams on root cause analyses. Excellent verbal/written communication, interpersonal skills, and presentation skills Preferred Qualifications 5+ years Automotive cybersecurity experience and familiarity with Security work products Familiarity with ISO 26262 Automotive Functional Safety standards is a plus Relevant Cybersecurity Certification is desired

ASIC RTL DESIGN ENGINEER (5 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 5 to 10 Years Openings: 4 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 5-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus