32 Ip Design Jobs

Expertise in ASIC RTL Design Expertise in ASIC IP Design Expertise in CDC and Lint tools Expertise in design and simulation tools Expertise in Video processing algorithms / interfaces Expertise in CXL / PCIe Protocol, 5G, Datacenter

Enphase Energy is a global energy technology company and a leading provider of solar, battery, and electric vehicle charging products. Since its establishment in 2006, Enphase has been at the forefront of innovation in solar power, enhancing its safety, reliability, and scalability. With the Enphase Energy System, individuals can generate, utilize, store, and even sell their own power. The company has a remarkable global presence, having shipped over 80 million products to 160 countries. In this role at Enphase, you will be part of a dynamic team focused on designing and developing next-generation energy technologies to contribute towards a sustainable future. The position requires your presence onsite for 3 days a week initially, with a plan to transition back to a full 5-day in-office schedule gradually. As an experienced SoC Verification engineer, you will join the Enphase team in Bangalore, India, contributing to the development of the next generation Control ASIC in 22nm technology. This ASIC incorporates the ARM CM4 core, necessitating expertise in this core. The SOC integrates safety and security features, demanding a comprehensive understanding of these SoC challenges. The Control ASIC includes various components such as the CPU, Analog Front End (AFE), Power Line Communications Modem (PLC), proprietary Power Production control block, and other peripherals. Reporting to the Senior Director of ASIC Engineering in Bangalore, you will collaborate with internal/contract verification resources, IP designers, and Full Chip RTL engineers to verify the new SOC design. Your responsibilities will involve defining the verification methodology and verifying the RTL developed by Enphase engineers and 3rd party IP. The ideal candidate for this role possesses: - Deep understanding and experience in SoC architecture and verification - Specific experience in verifying the ARM CM4 and associated IP like AHB, AXI, RAM and ROM controllers, and DMA controllers - Hands-on experience with RISC-V verification (preferred) - Proficiency in UVM using SystemVerilog, Coverage driven verification methods, and formal verification methods for IP/SoC functional verification - Knowledge of RTL verification methods, Gate-level verifications, and mixed-signal methodologies - Experience in bringing complex SOCs into production To be considered for this position, you should have a proven track record with at least 15+ years of experience in the field. Join Enphase Energy in shaping the future of energy technology and playing a significant role in building a sustainable future.,

Are you ready to take the next step in your career and contribute to cutting-edge ASIC and IP/SoC development We are looking for an experienced Design Engineer to join our team in Hyderabad. This is an exciting opportunity to work with a talented team on high-impact projects, pushing the boundaries of digital design in a collaborative and fast-paced environment. As a key technical contributor, you will work closely with ASIC engineering management to define and implement digital IP/SoC designs, and integrate these with third-party designs into customer ASICs and SoCs. You'll be part of a multi-site development team, ensuring the delivery of high-quality designs that meet customer requirements and solving complex technical challenges. Key Responsibilities: - Design & Implementation: Specify, micro-architect, implement, and perform design verification for complex RTL IP blocks, from basic SoC building blocks to advanced video processing and encoding/decoding logic. - IP Development Cycle: Take part in the full lifecycle of IP developmentfrom customer concept to backend layout and silicon validation. - Collaboration: Work closely with SoC architects to ensure designs align with project requirements and integrate seamlessly with the rest of the SoC. - Technical Guidance: Provide technical advice and solutions to design, verification, physical design, silicon validation, and production test teams. - Customer & Team Engagement: Analyse customer requirements and implement functional digital designs and integration flows for complex SoCs. Provide support for customer-facing technical discussions. - Tool & Script Development: Develop, maintain, and deploy proprietary scripts and tools for ASIC/SoC design and database management. Leverage industry-leading EDA tools for design quality assurance, power optimisation, and synthesis/timing analysis. - Continuous Learning: Stay up-to-date with the latest advances in engineering technologies and methodologies to maintain our competitive edge. - Mentorship: Coach junior engineers and support them in all aspects of design activities, including coding, synthesis, debug, DFT, and backend integration. - Technical Publications: Contribute to technical white papers, and provide sales support as part of a collaborative team. Key Relationships: Internal: Collaborate with Engineers, Senior Engineers, Principal Engineers, Project Managers, Sales, Finance, and HR teams. External: Technical communication with customers (minimal), and liaising with EDA Tool Vendors, Foundries, and Assembly Houses. What We're Looking For: Qualifications: Essential: - Degree/Masters or PhD in Electrical Engineering, Computer Science, or a related field. - Typically, 5+ years of relevant experience in digital design and IP/SoC development. Desirable: - A Masters or PhD in a related subject with practical experience of 5+ years. Skills & Experience: Essential: - Expertise in IP design, implementation, and verification. - Strong knowledge of RTL synthesis, performance, and power analysis. - In-depth understanding of digital design concepts and problem-solving capabilities. - Proficient in HDL coding (VHDL, Verilog, SystemVerilog). - System design knowledge, including clock domain management, reset schemes, and power management. - Experience with SoC level verification (HW/SW co-verification, multi-mode simulation, gate-level simulation). - Experience with design checking tools (Lint, CDC, LEC). - Strong communication skills and ability to provide technical guidance to junior engineers. Desirable: - Familiarity with ARM processor subsystems, video processing, bus protocols (AXI/AHB/ACE). - Experience with low power design methodology (UPF/CPF) and synthesis/timing analysis. - Experience with Tcl, Perl, Python, SystemC, IPXACT, and database management. - Familiarity with Linux software frameworks. Attributes: - Self-motivated with the ability to work independently and as part of a team. - Strong problem-solving skills and ability to adapt quickly to changing priorities. - Excellent attention to detail and time management skills. - A fast learner who thrives in a dynamic, collaborative environment.,

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture, and automation, you are well-equipped to excel in this role. Additionally, you should have 3 years of experience with Register-Transfer Level quality check tool flows such as Lint, Clock Domain Crossing, Reset Domain Crossing, and Synthesis. Preferred qualifications include experience with methodologies for RTL quality checks, IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols, and ASIC methodology. Additionally, experience with methodologies for low power estimation, timing closure, synthesis, and knowledge in areas such as Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin Multiplexing would be advantageous. Your responsibilities will involve defining microarchitecture details for the integration of Intellectual Property's (IPs) at the macro/Sub-System Workload Requirements Plan (SSWRP) level. You will be engaged in RTL development using SystemVerilog, debugging functional/performance simulations, and conducting RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, and Unified Power Format (UPF) checks. Furthermore, you will participate in synthesis, timing/power estimation, and FPGA/silicon bring-up processes. Join us in our mission to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create experiences that are radically helpful. By researching, designing, and developing new technologies and hardware, we aim to make computing faster, seamless, and more powerful, ultimately improving people's lives through technology.,

You have a great opportunity as a Project Management Specialist at Truechip, a leading provider of Design and Verification solutions in the VLSI industry. As a Project Management Specialist, you will be responsible for overseeing all aspects of multiple projects, ensuring they meet their goals on time and with high quality. Your role will involve organizing people, tasks, and resources to successfully conclude projects. Leading multiple project management team members and directly managing one or more projects will be part of your responsibilities. Truechip is looking for a leader with a Go-Getter attitude who can transform project teams and serve as a role model for team members to follow. Direct interaction with multiple customers and reporting directly to the CEO is also expected in this multifaceted role. You must have at least 10 years of experience, including managing a team of 50+ members. A Bachelor's degree in Engineering is required, while a Master's degree like an MBA is preferred. Possessing PMP/Prince 2 certification will be a plus. Key responsibilities include leading project planning and implementation, defining project scope and goals, scheduling timelines, coordinating project teams and customers, resource planning, risk assessment, project administration, budget management, and reporting to senior management. Maintaining strong customer relationships, ensuring high-quality deliverables, and tracking project performance are essential aspects of the role. To excel in this position, you must demonstrate high integrity, effective communication skills, and a proactive attitude. Experience in project management, creating delivery schedules, and engaging with international customers is crucial. Additionally, you should have strong organizational skills, the ability to manage multiple projects simultaneously, and a commitment to meeting customer timelines with high-quality results. Experience in semiconductor/SOC/IP/VIP design and verification, testbench architecture, verification planning, simulation tools, and handling ODCs for customers will be advantageous. International and domestic travel for short durations may also be required for this role. Truechip offers a dynamic work environment with a global presence across North America, Europe, and Asia. With over 11 years of experience in the VLSI industry, Truechip is committed to providing innovative solutions to its customers. For more information about Truechip, visit www.truechip.net.,

You are a highly motivated and energetic individual with a team-oriented approach, responsible for driving roadmaps in the IP/Subsystem domain. Your role involves delving deep into logic design, architecting, and developing complex IPs/Subsystems solutions. Working closely with a team of global experts in Systems and SoC Design functions, you will lead or address design/architectural challenges within the context of complex IPs and overall system level solutions. Your tasks will range from developing high-level specifications to actual design implementation. Your key responsibilities include owning and driving roadmaps for the complete IP/Subsystem domains portfolio within the global R&D team. You will perform benchmarks against other industry players to ensure differentiating features for customers with a high level of innovation. Architecting and designing complex IPs and Subsystems across various protocols required for Edge processing, Automotive Self-Driving Vehicles, In-Vehicle experience, Gateway Systems, Fail-Safe Subsystems (ASIL-D), etc., will be part of your role. You will be responsible for leading IPs/Subsystems from concept to design and development, achieving final design performance in an integrated system within aggressive, market-driven schedules. Ensuring quality adherence throughout the IP development cycle, analyzing existing processes, recommending and implementing process improvements, and driving and mentoring teams towards achieving Zero Defect designs are crucial aspects of your role. Additionally, you will be responsible for owning and driving global IP design methodologies across sites with global stakeholders. As a self-starter with over 18 years of experience, you should be able to architect and design complex IP designs/Subsystems with minimal supervision. Your expertise should include custom processor designs with key DSP functions, processor designs like RISC-V Core, cache-based subsystems, high-speed serial protocols, and associated challenges, understanding of key external memory interface protocols, microcontroller architecture, bus protocols, HDLs, scripting languages, and C/C++ for hardware modeling. Knowledge of end-to-end IP development flow, testbench and testplan development, and pre-silicon validation using FPGA/Emulation Board would be advantageous. In terms of soft skills, you should possess proficient skills in both written and verbal communication, with the ability to articulate well. Demonstrating a sense of ownership, engaging everyone with trust and respect, showcasing emotional intelligence, and embodying leadership values are essential for success in this role. You should have the ability to work effectively as part of a team, whether local, remote, or multisite.,

Role & responsibilities Must have exposure to NoC, IP/ SoC Design, CDC, AXI, Bus Interconnects

You will play a crucial role in developing Interface and Analog IPs for internal ASIC or external customers. This will involve hands-on experience with Hard Analog or PHY blocks on circuit design using the latest finfet nodes like 16nm and 7nm. Your responsibilities will include driving processes to establish a solid IP Development methodology for successful outcomes with customers. Additionally, you should be able to provide support for multiple customers and IP Deliveries, possessing strong knowledge in all aspects of IP integration such as logic design and verification, physical design, packaging, test, and characterization. To excel in this role, you should have a minimum of 6 years of experience in IP Design and delivery of complex analog, mixed signal IPs or PHYs. Previous exposure to DDR, HBM, and SerDes is highly preferred. A Masters Degree or equivalent in Electronics and Computer Engineering is the minimum educational qualification required, with a preference for a PhD. Expertise in the complete ASIC and IP development life cycle is essential, along with a desire for hands-on engineering experience throughout the ASIC/IP development flow. Excellent verbal and written communication skills are crucial, including the ability to engage effectively with customers and vendors. As part of our commitment to employee well-being and satisfaction, we offer a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), opportunities for advanced education from Premium Institutes and eLearning content providers, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. At Alphawave Semi, we prioritize Diversity & Inclusivity. We are an equal opportunity employer and encourage applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. If you require accommodation as a qualified job applicant, we will work with you to provide reasonable accommodations tailored to your specific needs. If your application is selected to proceed in our hiring process, you will have the opportunity to request accommodations.,

As the Lead for the implementation of Ceremorphic AI hardware architecture and design of memory technologies, you will play a crucial role in integrating knowledge from various fields like AI, compilers, computer architecture, analog circuits, and memories. Your responsibilities will revolve around designing memory technologies including SRAM, Register Files, ROM generators, and other related components. Your key requirements for this position include a fundamental understanding of bit cell characteristics such as SNM, WM, Cell current, Standby current, data retention, among others. You should also possess expertise in dealing with process variability and circuit reliability issues that impact power consumption, speed, area utilization, and yield. A strong grasp of custom circuit design and layout in finFET-based CMOS technologies is essential for success in this role. Additionally, you are expected to have proficiency in critical path modeling using various models like RC, C, Pi, ladder, distributive, and others. Familiarity with scripting languages such as Python or Perl, as well as the UNIX operating system, will be beneficial. Demonstrated technical leadership skills and a solid foundation in semiconductor physics are also crucial. Moreover, a good understanding of semiconductor physics, along with knowledge and interest in IC technology and IP design, is mandatory for this position. Your ability to lead and drive the implementation of cutting-edge memory technologies within the Ceremorphic AI hardware framework will be pivotal in advancing the company's technological capabilities.,

Build your career with Sykatiya Technologies, a company that values Technical Ability and the Attitude of its highly talented team. Our team consists of skilled engineers and experts from various domains such as Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently looking for candidates for the role of RTL/ IP Design with 3-12 years of experience to join our team in Bangalore. As an ideal candidate, you should have at least 5 years of experience in digital ASIC front-end design. You should possess a thorough understanding of design flows including RTL (VHDL, Verilog, and/or SystemVerilog). Experience with simulation tools like Questa or Xcelium and logic synthesis tools such as Synopsys DC is highly desirable. Candidates applying for this position should also have experience working with embedded microcontrollers and AMBA bus systems. A Bachelor's degree in science or engineering and proficiency in English communication are essential requirements for this role. If you are passionate about ASIC design and meet the above qualifications, we encourage you to apply and be a part of our dynamic team at Sykatiya Technologies.,

Job Summary 8-12 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, Verification and Debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers.

Job description Seize the opportunity to work with the team responsible for RTL logic design and microarchitecture of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for client and server chipsets.Candidate will be responsible for logic design and development, responsibilities including but not limited to: Develops the logic design, register transfer level (RTL) coding, and simulation for an IP design. Participates in the definition of microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for meet the design specification requirements. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Supports SOC to integrate and validate the IP on need basis. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications : BE/ME/Btech/ Mtech in computer science eng or electronics and Communications. The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent. The candidate should have successful track record of hardware development experience and demonstrated technical leadership skills. The candidate must have demonstrated the ability to solve highly complex technical problems with excellent communication skills. The candidate must also have demonstrated strong ethical standards. Must also be able to perform in a highly ambiguous and dynamic business environment. Skills : Relevant experience with skills in ASIC IP design flows, RTL coding and Globals (Clocking, Boot/ Reset/Fabrics, DfD, Fuse, etc) with experience in CDC, linting, spyglass, micro-architecture. Experience in subsystem design and IO protocols such as AMBA, USB, PCIe, UCIe, UFS, SATA, UART, SPI, I2C, I3C etc is a plus. Other technical requirements: 3 to 8 years of relevant pre-silicon logic design experience in ASIC domain. Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/ Shell scripting, Synopsys tools, RTL model build, design-for-test, design-for-verification. Experienced in EDA tools & flows such as Spyglass VCLINT, VCLP, VC-CDC, SG-DFT, Design Complier, Calibre, Fishtail, FEV, ATPG etc. Experienced in developing micro-architecture based on High Level Architecture specifications. Experienced in VLSI or Structural and Physical design flow and methodology. Experienced in Power-aware design and reviewing validation flows. Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

Job description Role & responsibilities Performs functional logic verification of a block, subsystem, and SoC related to DCAI flagship AI products to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Preferred candidate profile Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 5+ years of technical experience. Related technical experience should be in/with: Silicon Design and/or Validation/Verification. Design/Verification with developing, maintaining, and executing complex IPs and/or SOCs. Design/Verification exposure for Ethernet or PCIe Subsystem involving full protocol stack - Transaction layer, Data Link Layer and PHY Layer Design/verification exposure for Industry standard BUS topologies such as AMBA AXI/AHB/APB , I2C, SPI, JTAG, CoreSight Debug and Trace OVM, UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation.

Job description ISSP FPGA prototyping delivers Intel's core products, therefore you will have a unique opportunity to take part in major activities that affect the entire organization and the high-tech world.Our FPGA design verification team is in charge of validating infrastructure designs used to prototype cutting edge Intel client, devices and data centers chips.We are looking for great, highly motivated problem-solvers seeking to make significant contributions and impact on the projects they work on.In your role you will plan, design and execute scalable and robust verification environments, learn complex digital computers flows and simulate the behavior of the RTL design in purpose of debug and development using advanced verification methodologies. Qualifications Studying towards a B.Sc. or MSc in Computer Science / Electrical Engineering / Computers Engineeringsome experience with OOP (C++, Java...)some understanding of chip design frontend flow (design/validation/synthesis)any relevant chip design / verification experience is a big advantage

You are an experienced RTL/FPGA Design Engineer with a minimum of 3 - 7 years of experience in the VLSI domain. You hold a BE/B.Tech degree in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or a closely related field from a recognized university with a strong academic background. Your role will be based in Ahmedabad or Bangalore. In this role, you will be responsible for RTL programming using Verilog/System Verilog or VHDL, possessing knowledge of the complete FPGA Design Development flow. You should be proficient with FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will engage in functional verification using Verilog/System Verilog or VHDL, optimize RTL code to meet timings and on-chip resources, and support all phases of FPGA-based product development activities. System Architecture Design, testing, and troubleshooting of hardware will also be part of your responsibilities. To excel in this position, you must have experience with Verilog/SystemVerilog or VHDL for design and verification, along with a deep understanding of FPGA design flow/methodology, IP integration, and design collateral. You should be capable of developing small IP blocks from scratch and conducting basic functional verification. Familiarity with protocols like SPI, I2C, UART, and AXI, as well as knowledge of Altera Quartus II Tool, Questasim, Modelsim, Xilinx tools like ISE and Vivado, and Microsemi tools like Libero, are essential. Understanding of USB, Ethernet, and external memories such as DDR, QDR RAM, and QSPI-NOR based Flash is also required. In terms of personal competencies, you should be self-motivated to learn and contribute, able to work effectively with global teams, and willing to collaborate in a team-oriented environment. Prioritization and execution of tasks to achieve goals in a fast-paced environment, along with strong problem-solving skills, are valuable assets. Your passion for writing clean and neat code that aligns with coding guidelines will be highly appreciated. If you meet these qualifications and are excited about the opportunity to work in the VLSI domain as an RTL/FPGA Design Engineer, we encourage you to apply now.,

KEY RESPONSIBILITIES: Defines, plans and drives projects and program plans based on management and senior technical guidance Possesses a thorough knowledge of the principles of project management andcanapply them effectively on small to large size projects Has responsibility for projects or processes of significant technical importance and for results that cross engineering project areas Initiates significant changes to existing processes and methods to improve project and teamefficiency Creates and maintains project management artifacts such as schedule, resource and resource forecast, risk and issues logs Provides unique views of project status updates and facilitates cross development team dependencies and communications Identify action or mitigation plans for issues orrisksthat arise during the project lifecycle Collaborates with core teams and execution teams to identify areas that require special attention or escalations to identify corrective actions Collect, analyze, organize and publish work performance data via dashboards and recurring statusreports Detail oriented with strong analytical and debugging skills Engage with IP and SOC teams to drive closure to IP RTL deliverables PREFERRED EXPERIENCE: Detailed oriented, self-driven with a strong sense of pride and ownership. At least 15 years of experience focused on IP and/or SOC design, verification with successful completion of multiple ASICs that are in production Strong organizational, problem-solving, interpersonal, presentation, written and verbal communication skills Ability to build relationships and work effectively as a self-starter and as part of a team Proactively involve team members in planning, decision-making and execution efforts People management experience is desirable Excellent verbal and written communication skills to handle all levels of interaction, including executive level Horizontal leadership/Matrix management experience Technicalprogrammanagementandcustomerrelationshipmanagement Collaborate in problem solving and mitigating risks with Engineering, Program/Project Management, Business Units and Product Management - both internal and external Strong knowledge of productivity and project tools including Jira, Confluence, Microsoft Office Suite Preferably with GPU background ACADEMIC CREDENTIALS: Bachelors orMastersdegree in Computer/Electrical Engineering Formal project management education, PMP / Scrum Master

You will be responsible for designing and developing Debug IPs focusing on CoreSight IP design. Your role will involve ensuring that the Debug IPs meet the required specifications and performance standards. You will utilize your expertise in RTL design using Verilog and/or SystemVerilog for complex SoC development. Additionally, you will apply your knowledge of Arm-based designs and/or Arm System Architectures to develop and optimize IPs. Collaboration with cross-functional teams, SoC integration & Architecture teams is essential to ensure successful IP delivery within specified timelines. Implementing rigorous verification processes to ensure that the IPs meet all functional and performance requirements is a key aspect of the role. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in RTL design for complex SoC development using Verilog and/or SystemVerilog is required. A strong understanding of Arm-based designs and/or Arm System Architectures is essential. Proficiency in IP design, verification, and delivery, with a focus on Debug IPs, is also a key requirement. Excellent communication and collaboration skills are necessary to effectively work with cross-functional teams. Preferred skills for this role include experience with CoreSight based Debug IP design and strong problem-solving and analytical skills.,

ASIC RTL DESIGN ENGINEER (4 to 10 Years) IP/SoC Design Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune/Chennai/Noida] Experience: 4 to 10 Years Openings: 6 Positions Job Description Sr RTL Design Engineer We are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in designing state of the art solutions for automotive camera and display systems. Responsibilities Microarchitecture definition and RTL implementation ensuring optimal performance, power, area. Collaborate with software teams to define configuration requirements, verification collaterals etc. Work with verification teams on assertions, test plans, debug, coverage etc. Proficiency in Verilog/System Verilog Very google understanding of ASIC design methodologies Qualifications and Preferred Skills Graduate/Post Graduate/PhD in Electrical/Electronics 4-10 years hands-on experience in microarchitecture and RTL development Proficiency in developing micro-architecture from the design requirements, defining the H/W- S/W interface. In-depth understanding of MIPI CSI and DSI protocols Experience designing IP blocks for video and audio design Proficiency in Verilog, System Verilog Familiarity with industry-standard EDA tools and methodologies Experience with large high-speed, pipelined, and low power designs Excellent problem-solving skills and attention to detail Strong communication and collaboration skills Experience in designs complying to automotive functional safety will be a plus

As a VLSI Design Engineer at Kinara, you will be part of a dynamic team focused on edge AI technology, pushing the boundaries of what's achievable in machine learning and artificial intelligence. You will contribute to the development of state-of-the-art AI processors and high-speed interconnects, ensuring unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. Your role will involve working on cutting-edge semiconductor projects, requiring a blend of technical expertise, problem-solving skills, and collaborative teamwork. Your responsibilities will include defining micro-architecture and creating detailed design specifications, developing RTL code based on system-level requirements using Verilog, VHDL, or SystemVerilog, implementing complex digital functions and algorithms in RTL, and executing comprehensive test plans to verify RTL designs. You will optimize designs for power, performance, and area constraints, conduct simulation and debugging activities to ensure design accuracy, collaborate with verification engineers to develop test benches and validate RTL against specifications, and apply your strong understanding of digital design principles and concepts. To excel in this role, you should possess proficiency in writing and debugging RTL code, experience with synthesis, static timing analysis, and linting tools, familiarity with scripting languages like Python, Perl, or TCL for automation, and expertise in processor subsystem design, interconnect design, or high-speed IO interface design. A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with 5+ years of experience in RTL design and verification, is required. Proven experience in digital logic design using Verilog, VHDL, or SystemVerilog, familiarity with simulation tools such as VCS, QuestaSim, or similar, and hands-on experience with RTL design tools like Synopsys Design Compiler and Cadence Genus is preferred. At Kinara, we offer an innovative environment where technology experts and mentors collaborate to tackle exciting challenges. We believe in sharing responsibilities and valuing diverse viewpoints. If you are passionate about making a difference in the field of edge AI technology, we invite you to join our team and contribute to creating a smarter, safer, and more enjoyable world. Your application is eagerly awaited as we look forward to reviewing your qualifications and experiences. Make your mark with us at Kinara!,

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: FPGA Design engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Strong in digital design. Strong in Xilinx Vivado IP & IPI tools till bit-generation. Knowledge of VHDL/Verilog/System Verilog. Knowledge of Validating IP/IP Example designs on Xilinx boards, debugging of failures on target boards, board bring up. Proficiency in Linux environment. Good communication skills. Basic Job Deliverable: RTL coding, IP design, Modify/update existing IP as per requirements. Qualification: Bachelors/Master’s in ECE TekWissen® Group is an equal opportunity employer supporting workforce diversity.

Qualcomm India Private Limited is looking for a skilled Program Manager to join their Engineering Services Group. As a Program Manager, you will be responsible for developing, defining, and executing plans of record, including schedules, budgets, resources, deliverables, and risks. Your role will involve monitoring and driving the program from initiation through delivery, interfacing with internal and external stakeholders across functions on technical matters as needed. You will also be accountable for monitoring budget/spending, on-time delivery, and achieving program milestones, as well as representing the program and driving alignment across stakeholders. Your key responsibilities will include establishing day-to-day operational objectives, organizing interdepartmental activities to ensure the completion of the program on schedule, managing change control and escalations, assessing program/initiative issues and areas of risks, and collaborating with various stakeholders to resolve problems. You will be expected to identify risks, clearly communicate goals and results, conduct team meetings, document issues, and keep the extended team informed of the status and health of IP development/delivery. Additionally, you will monitor and ensure product/program/project schedule compliance and interact with senior management and executives on respective functional areas. The ideal candidate should possess a Bachelor's degree in Electrical/Electronic Engineering, Computer Science, or a related field. You must have experience in complete IP lifecycle development, domain knowledge on IP design, deep technical expertise on various components like DLL, PLL, LDO, ADC, DAC, and sensor design, verification, and bring-up. It is essential that you have worked on RTL to GDS flow of digital IPs, and spec to GDS flow for analog and mixed signal IPs, along with complete ASIC lifecycle development. Moreover, you should have strong Microsoft tools skills (Excel, Powerpoint, Word, MPP, PowerBI), proven analytics skill in the VLSI domain, established interpersonal skills, the ability to communicate effectively at all levels, and the capability to synchronize and motivate engineering leads to attain common goals. While not mandatory, it would be advantageous to have domain knowledge of PDK components, IP quality assurance plan, quality control, test Chip design management, and experience with tools like MS_PowerBI, JIRA, and Confluence. A total of 10+ years of experience, with at least 4 years in program management, is desired. If you have a Master's degree in Engineering, Computer Science, or a related field, hold a PMP Certification, and have 7+ years of program management experience, you are encouraged to apply. Experience in a role requiring interaction with senior leadership, working in a large matrixed organization, and using program management tools such as dashboards and Gantt charts would be considered a plus. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Applicants are expected to comply with all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs directly at Qualcomm, and staffing and recruiting agencies are not authorized to use the site or submit profiles on behalf of candidates. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, please reach out to Qualcomm Careers.,

As a highly experienced Verification Engineer at our dynamic team, you will drive innovation in advanced verification methodologies for complex semiconductor designs. Your key responsibilities will include leading the deployment of verification tools, platforms, and strategies for complex IPs, driving simulation-based and hardware-assisted verification efforts, applying expertise in various verification technologies, developing and enhancing verification methodologies, collaborating cross-functionally with IP design and DV teams, and mentoring junior engineers to foster a culture of technical excellence. You should have 10+ years of experience in verification engineering for complex hardware systems, deep expertise in simulation and debug, hands-on experience with Static/Formal verification tools and methodologies, exposure to hardware-assisted verification environments, strong analytical and problem-solving skills, a degree in Electrical Engineering, Computer Engineering, or related field, familiarity with industry-standard verification languages, experience with scripting and automation, and a track record of technical leadership and cross-functional collaboration. Join our team at Synopsys and be part of an environment that values agility, courage, excellence, and trust. You will have the opportunity to work on cutting-edge technology and make a real impact.,

You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC project, expertise in IP design, subsystem design, SoC integration, and successful leadership of a team to deliver projects on time. If you are interested in this position, please share your updated CV with gayatri.kushe@tessolve.com or connect on 6361542656.,

Qualcomm India Private Limited is looking for a Program Manager to join the Engineering Services Group. As a Program Manager, you will be responsible for developing, defining, and executing plans of record, including schedules, budgets, resources, deliverables, and risks. You will monitor and drive the program from initiation through delivery, interacting with internal and external stakeholders across functions on technical matters as needed. Additionally, you will monitor budget/spending, on-time delivery, and achievement of program milestones, representing the program and driving alignment across stakeholders. Your responsibilities will include establishing day-to-day operational objectives, organizing interdepartmental activities to ensure the program is completed on schedule, managing change control and escalations, assessing program/initiative issues and areas of risks, and working with various stakeholders to resolve problems. You will also identify risks, communicate goals and results clearly, conduct team meetings, document issues, and keep the extended team informed of the status and health of IP development/delivery. Monitoring and ensuring product/program/project schedule compliance, interacting with senior management and executives on respective functional areas, and motivating engineering leads to attain common goals are also key aspects of this role. The minimum qualifications for this position include a Bachelor's degree in Electrical/Electronic Engineering, Computer Science, or a related field, along with at least 4+ years of Program Management or related work experience. You should have deep technical expertise in areas such as DLL, PLL, LDO, ADC, DAC, and sensor design, verification, and bring-up. Experience in complete ASIC lifecycle development, RTL to GDS flow of digital IPs, spec to GDS flow for analog and mixed signal IPs, and MSIP design and verification is essential. Strong Microsoft tools skills, proven analytics skill in the VLSI domain, and established interpersonal skills are also required. Preferred qualifications include a Master's degree in Engineering, Computer Science, or a related field, PMP Certification, and 7+ years of Program Management or related work experience. Experience working in a role requiring interaction with senior leadership, a large matrixed organization, and program management tools such as dashboards and Gantt charts is desired. If you have a disability and need accommodations during the application/hiring process, Qualcomm is committed to providing accessible support. Please email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number for assistance. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking a job at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For more information about this role, contact Qualcomm Careers.,

This is a verification-focused individual contributor's role within the DesignWare IP Verification R&D team at our Bangalore Design Center, India. As a part of this team, you will be responsible for implementing state-of-the-art Verification environments for the DesignWare family of synthesizable cores and executing Verification tasks for the IP cores. You will collaborate closely with the RTL design team and work alongside a global team of expert Verification Engineers. The domains you will be working on include USB, PCI Express, Ethernet, and AMBA. Your responsibilities in this role will encompass a variety of tasks such as Test planning, Test environment coding at both unit and system levels, Test case coding and debugging, FC coding and analysis, and achieving quality metric goals and regression management. To be considered for this position, you should have a BS/BE in EE with 7+ years of relevant experience or an MS with 6+ years of relevant experience in IP cores verification and/or SOC verification. You should possess experience in developing HVL-based test environments, creating and implementing test plans, and extracting verification metrics like functional coverage. Additionally, you must have proficiency in HVL coding for Verification and hands-on experience with industry-standard simulators such as VCS, NC, MTI, along with relevant debugging tools. Exposure to verification methodologies like UVM/VMM/OVM is essential, and familiarity with HDLs such as Verilog and scripting languages like Perl is highly desired. A basic understanding of functional & code coverage, exposure to IP design and verification processes including VIP development, and good written and oral communication skills are crucial for this role. You should also be able to demonstrate strong analysis, debugging, problem-solving skills, and be self-driven. Join our Silicon IP business, where we focus on integrating more capabilities into an SoC faster. Synopsys offers the world's broadest portfolio of silicon IP, pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors. We aim to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and bring differentiated products to market quickly with reduced risk. At Synopsys, we are at the forefront of innovations that reshape the way we live and work, including self-driving cars, artificial intelligence, the cloud, 5G, and the Internet of Things. Our advanced technologies for chip design and software security power these breakthroughs. If you are passionate about innovation, we look forward to meeting you.,