124 Apb Jobs

Job Role 1. Design and manage cloud-based systems on AWS. 2. Develop and maintain backend services and APIs using Java. 3. Basic knowledge on SQL and able to write SQL queries. 4. Good hands on Docker file and multistage docker 5. Implement containerization using Docker and orchestration with ECS/Kubernetes. 6. Monitor and troubleshoot cloud infrastructure and application performance. 7. Collaborate with cross-functional teams to integrate systems seamlessly. 8. Document system architecture, configurations, and operational procedures. Need Strong Hands-on Knowledge: * ECS, ECR, NLB, ALB, ACM, IAM, S3, Lambda, RDS, KMS, API Gateway, Cognito, CloudFormation. Good to Have: * Experience with AWS CDK for infrastructure as code. * AWS certifications (e.g., AWS Certified Solutions Architect, AWS Certified Developer). * Python Mandatory Competencies Cloud - AWS - ECS Cloud - AWS - Amazon Elastic Container Registry (ECR), AWS Elastic Kubernetes Service (EKS) Cloud - AWS - Amazon API Gateway Beh - Communication Cloud - AWS - AWS S3, S3 glacier, AWS EBS

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

About The Role About The Role Should be good in Integration of SOC & RTL coding. Should be aware of SOC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills: VHDL, Verilog,Micro-architecture, R TL coding,CDC, Lint, Synthesis, STA,IP development , SoC integration,VCLP,scripting -Perl,Python,Shell, and Tcl. Secondary Skills: Synopsis/Cadence tool flow,ARM Coretex,DMA, DDR, SPI, I2C, UART,AHB/AXI/APB,Ethernet, USB, PCIe,Mipi CSI/DSI, LPDDR. Education B.E/B.Tech/ Any Engineering.

What we’re looking for The Infrastructure team is looking for a Software Engineer with deep experience in and passion for cloud systems and software security. Our team works with teams across the company to help ensure that SurveyMonkey’s cloud infrastructure and security standards and practices are world-class. You’ll have the opportunity to develop infrastructure tools, and help teams implement them. What you’ll be working on Maintain and operate AWS environments with well established best practices Partnering with teams across the company include Application Engineering, Security Operations, and Product to provide the technical foundations of our cloud infrastructure and security systems Analyzing our existing systems, and designing and implementing tools to maintain internal security guardrails Providing both technical guidance and mentorship to developers in adopting good security practices in their feature development Developing tools to help SurveyMonkey comply with privacy regulations across the globe We’d love to hear from people with 8+ years of experience with application development 4+ years of experience with AWS, including but not limited to heavy experience with IAM, ALB, S3, AWS Lambda, CloudWatch, Transit Gateway, VPC, CloudFront, Route 53, Cloud Map, and VPN Proficient in AWS security technologies including GuardDuty, ACM, Shield, WAF, and Firewall Manager Demonstrable experience leveraging Configuration Management tooling such as Terraform, and proven strategies for maintaining large infrastructure-as-code deployments A strong understanding of web application security risks and control (e.g., OWASP Top 10) Proficient in Python or equivalent; NodeJS experience a plus Familiarity with privacy regulations like GDPR, CCPA, etc is a plus This opportunity is hybrid and requires you to work from the SurveyMonkey office in Bengaluru 3 days per week. #LI-HYBRID

Job Title: Lead Design Verification Engineer Location: m Bangalore Job Type: Full-time Experience Level: 7+ years Department: Hardware Engineering / VLSI Design Job Summary: We are seeking a highly experienced Lead Design Verification Engineer to lead verification efforts for complex digital designs. The ideal candidate will drive testbench architecture, verification planning, and execution for ASIC/SoC or FPGA-based designs, ensuring first-time-right silicon or system functionality. You will work closely with RTL design, DV, and system engineering teams to deliver high-quality products. Key Responsibilities: Lead and drive the verification strategy, planning, and execution for IP, subsystem, or full-chip level. Define and implement constrained-random, directed, and coverage-driven verification methodologies (UVM/SystemVerilog preferred). Develop and maintain scalable and reusable testbench components. Mentor and guide junior verification engineers in testbench architecture, debugging, and coverage closure. Collaborate with RTL designers, architects, and firmware/software teams to understand design intent and develop test plans. Own and track functional coverage metrics and ensure 100% coverage goals are met. Drive regular reviews of verification status, risks, and issues with stakeholders. Support post-silicon validation teams with test vectors, debugging, and failure analysis. Required Qualifications: Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 7+ years of industry experience in digital design verification. Strong expertise in SystemVerilog, UVM, and advanced verification methodologies. Experience in testbench architecture, test planning, and constrained-random stimulus generation. Solid understanding of digital design concepts, SoC/ASIC design flows, and bus protocols (e.g., AXI, AHB, PCIe, etc.). Hands-on experience with simulation tools (VCS, Questa, etc.) and coverage analysis tools. Excellent debugging and problem-solving skills using waveform viewers and assertion-based techniques. Familiarity with scripting languages such as Python, Perl, or TCL for automation. Strong communication and leadership skills with experience leading small to mid-sized teams. Preferred Qualifications: Experience in formal verification techniques. Experience with emulation, FPGA prototyping, or post-silicon bring-up. Exposure to power-aware or low-power verification (UPF/CPF). Knowledge of hardware security, safety, or compliance standards (ISO 26262, DO-254, etc.) is a plus. Familiarity with CI/CD flows and version control (Git, Jenkins, etc.). Why Join Us: Work on cutting-edge technologies and next-generation chip designs. Opportunity to lead high-impact projects and influence verification strategy. Collaborative and innovative work environment. Competitive salary, benefits, and career growth opportunities.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV Experience in Logic design/micro-architecture/RTL coding is a must. Must have hands on experience with design and integration of complex multi clock domain blocks Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Work closely with the Design verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is preferable Experience in Synthesis / Understanding of timing concepts for ASIC is must Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

General Summary: Responsibilities will include to be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 3-6 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB/PCIE/Ethernet preferred. Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Strong experience in micro architecting RTL design from high level design specification. Excellent problem solving skills, strong communication and team work skills are mandatory. Self-driven, needs to work with minimum supervision. Experience in System Verilog, Verilog, C/C++, Perl and Python is a plus Ability to lead a small design team. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

You have an exciting opportunity with Tessolve Semiconductor in Bangalore for the roles of RTL Design Engineer and Design Verification Engineer. For the position of RTL ASIC Engineer, you should have at least 7 years of work experience in ASIC/IP Design with expertise in Logic design and RTL design. Your responsibilities will involve IP design and integration, along with proficiency in tools such as Lint and CDC for ASIC development. Knowledge of Synthesis and understanding of timing concepts would be advantageous. Additionally, familiarity with AMBA protocols like AXI, AHB, APB, and SoC clocking/reset architecture is preferred. As a Design Verification Engineer, you are required to have 5 to 20 years of experience. You should be well-versed in IP verification using SV/UVM, SOC Verification using C/SV, and Third Party VIP Integration. Your expertise in Interconnect Protocols such as AHB, AXI, APB, SOC Interfaces like GPIO, SPI, I2C, UART, High-Speed Serial Interfaces including PCIe Gen 3/4, USB, MIPI, and Memory Interfaces like DDR or HBM I/O will be crucial. Proficiency in Coverage Closure (Code, Functional, Toggle) and tools like Synopsys VCS or Cadence Incsive is essential. Experience in Technical Documentation, Foundry Porting, and Technology Library Conversion related to Verification will be advantageous. If you meet the requirements and are interested in these positions, please share your updated CV with Gayatri Kushe at gayatri.kushe@tessolve.com or contact at 6361542656. Thank you for considering this opportunity with Tessolve Semiconductor.,

The ideal candidate for this role should possess a strong understanding of RTL design and microarchitecture of IPs, with the ability to integrate them into sub-systems and SoCs. Responsibilities include defining the Uarch of SoC IPs, conducting RTL development, and ensuring the quality of RTL through checks such as Clock Domain Crossing (CDC) check, Lint, Design for Testability (DFT), and Low Power Checks. Additionally, the candidate will be involved in RTL synthesis, STA support, and provide pre and post-silicon functional verification support. Collaboration with different domain teams is essential for successful execution of tasks, along with a solid understanding of DDR knowledge. The candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, coupled with 6-10 years of experience in IP/SoC Design. Proficiency in SoC design and integration for complex SoCs is a prerequisite, while experience in Synthesis and understanding of timing concepts is considered advantageous. Candidates are expected to have knowledge of AMBA protocols such as AXI, AHB, and APB, in addition to expertise in SoC clocking/reset architecture. Strong RTL design and coding skills in Verilog, System Verilog, VHDL, etc., are required, along with experience in micro-architecture and design of digital IPs and subsystems.,

The Team: The OSTTRA Technology teamis composed of Capital Markets Technology professionals, who build,supportand protect the applications that operate our network. The technology landscapeincludeshigh-performance, high-volume applications as well as compute intensive applications,leveragingcontemporary microservices, cloud-based architectures The Impact: Together, we build, support, protect and manage high-performance, resilient platforms that process more than 100 million messages a day. Our services are vital to automated trade processing around the globe, managing peak volumes and working with our customers and regulators to ensure the efficient settlement of trades and effective operation of global capital markets Whats in it for you: We are looking for highly motivated technology professionals who will strengthen our specialisms, and championour uniqueness to create a company that is collaborative, respectful, and inclusive to all. You will have 5-10 years experience of working with Network Infrastructure to meet the needs of our expanding portfolio of Financial Services clients .This is an excellent opportunity to be part of a team based out of Gurgaon and to work with colleagues across multiple regions globally. Responsibilities: As a network engineer you will be a member of OSTTRAs global network infrastructure team that is responsible for our office, data Centre and cloud network infrastructure. You will be involved in all aspect of our network infrastructure lifecycles and work with supporting and maintaining our network. Support new projects as a network resource What Were Looking For: A degree in Computer Science or a related subject or the equivalent in knowledge and work experience A minimum of 5 years of experience with networks operations and architecture. Experience with network security, firewalls, VPNs and IDS/IPS solutions. Extensive experience in protocols such as BGP and MPLS Experience from working with Juniper, Palo-Alto Networks, F5, Cisco, Fortinet. Self-motivated and great under pressure. Big-picture understanding of the networking concepts behind virtual environments and various hybrid cloud initiatives Excellent verbal and written communication skills Experience from configuration management and change management. Working experience in various AWS services such as EC2, TGW, ALB, VGW, VPC, Direct-Connect, ELB, Cloud-formation Experience using network automation tools such as Terraform, Ansible, Git and Python. Excellent AWS Troubleshooting. Experience of working with Docker and Kubernetes Experience with working with data centres in US & UK. Working experience from the financial industry. Hands-on experience of Linux operating systems.

About the Role: OSTTRA India The Role: Network Engineer The Team: The OSTTRA Technology teamis composed of Capital Markets Technology professionals, who build,supportand protect the applications that operate our network. The technology landscapeincludeshigh-performance, high-volume applications as well as compute intensive applications,leveragingcontemporary microservices, cloud-based architectures The Impact: Together, we build, support, protect and manage high-performance, resilient platforms that process more than 100 million messages a day. Our services are vital to automated trade processing around the globe, managing peak volumes and working with our customers and regulators to ensure the efficient settlement of trades and effective operation of global capital markets Whats in it for you: We are looking for highly motivated technology professionals who will strengthen our specialisms, and championour uniqueness to create a company that is collaborative, respectful, and inclusive to all. You will have 5-10 years experience of working with Network Infrastructure to meet the needs of our expanding portfolio of Financial Services clients .This is an excellent opportunity to be part of a team based out of Gurgaon and to work with colleagues across multiple regions globally. Responsibilities: As a network engineer you will be a member of OSTTRAs global network infrastructure team that is responsible for our office, data Centre and cloud network infrastructure. You will be involved in all aspect of our network infrastructure lifecycles and work with supporting and maintaining our network. Support new projects as a network resource What Were Looking For: A degree in Computer Science or a related subject or the equivalent in knowledge and work experience A minimum of 5 years of experience with networks operations and architecture. Experience with network security, firewalls, VPNs and IDS/IPS solutions. Extensive experience in protocols such as BGP and MPLS Experience from working with Juniper, Palo-Alto Networks, F5, Cisco, Fortinet. Self-motivated and great under pressure. Big-picture understanding of the networking concepts behind virtual environments and various hybrid cloud initiatives Excellent verbal and written communication skills Experience from configuration management and change management. Working experience in various AWS services such as EC2, TGW, ALB, VGW, VPC, Direct-Connect, ELB, Cloud-formation Experience using network automation tools such as Terraform, Ansible, Git and Python. Excellent AWS Troubleshooting. Experience of working with Docker and Kubernetes Experience with working with data centres in US & UK. Working experience from the financial industry. Hands-on experience of Linux operating systems. The Location: Gurgaon, India OSTTRAis a market leader inderivatives post-trade processing, bringing innovation, expertise, processes and networks together to solve the post-trade challenges of global financial markets. OSTTRA operates cross-asset post-trade processing networks,providinga proven suite of Credit Risk, Trade Workflow and Optimisation services.Together these solutions streamline post-trade workflows, enabling firms to connect to counterparties and utilities, manage credit risk, reduce operationalrisk andoptimiseprocessingtodrive post-trade efficiencies. OSTTRA was formed in 2021 through the combination of four businesses that have been at the heart of post trade evolution and innovation for the last 20+ years: MarkitServ, Traiana, TriOptima and Reset. These businesses have an exemplary track record of developing and supporting critical market infrastructure and bring together an established community of market participants comprisingall trading relationships and paradigms, connectedusingpowerful integration and transformation capabilities. About OSTTRA Candidates should note that OSTTRAis an independentfirm, jointly owned by S&P Global and CME Group. As part of the joint venture, S&P Global providesrecruitmentservices to OSTTRA - however, successful candidates will be interviewed and directly employed by OSTTRA, joiningour global team of more than 1,200 posttrade experts. OSTTRA was formed in 2021 through the combination of four businesses that have been at the heart of post trade evolution and innovation for the last 20+ years: MarkitServ, Traiana, TriOptima and Reset. OSTTRA is a joint venture, owned 50/50 by S&P Global and CME Group. Joining the OSTTRA team is a unique opportunity to help build a > We take care of you, so you cantake care of business. We care about our people. Thats why we provide everything youand your careerneed to thrive at S&P Global. Health & Wellness: Health care coverage designed for the mind and body. Family Friendly Perks: Its not just about you. S&P Global has perks for your partners and little ones, too, with some best-in class benefits for families. Recruitment Fraud Alert: If you receive an email from a spglobalind.com domain or any other regionally based domains, it is a scam and should be reported to . S&P Global never requires any candidate to pay money for job applications, interviews , offer letters, pre-employment training or for equipment/delivery of equipment. Stay informed and protect yourself from recruitment fraud by reviewing our guidelines, fraudulent domains, and how to report suspicious activity .

Description: Java developers with Legacy code optimization modernization and onpremises cloud migration AWS Requirements: Experienced in designing scalable, cost-effective, and efficient cloud solutions using AWS services and best practices. A strong foundation in AWS services such as ALB, ECS, S3, ElastiCache, IAM, CloudWatch, and S3 Glacier, with the ability to design cloud-native applications. Experience in deploying infrastructure through automation tools like AWS CloudFormation and Terraform. Involved in migrating existing on-premises applications to AWS, as well as modernizing legacy systems Proven expertise in Java development, with a strong understanding of Java 11+ and experience in building scalable backend systems. Experience in modernizing legacy systems, with a focus on optimizing performance, scalability, and cost-efficiency. Proficiency in CI/CD pipelines using tools like Jenkins, ensuring efficient delivery of high-quality software. Strong database expertise, including experience with relational and NoSQL databases, along with skills in database design, optimization, and management. Proficiency in Infrastructure as Code (IaC) tools such as Terraform or AWS CloudFormation. Nice to Have: we leverage the latest technologies, including the AI revolution. Experience with AI tools that enhance productivity is highly desired. Job Responsibilities: Experienced in designing scalable, cost-effective, and efficient cloud solutions using AWS services and best practices. A strong foundation in AWS services such as ALB, ECS, S3, ElastiCache, IAM, CloudWatch, and S3 Glacier, with the ability to design cloud-native applications. Experience in deploying infrastructure through automation tools like AWS CloudFormation and Terraform. Involved in migrating existing on-premises applications to AWS, as well as modernizing legacy systems Proven expertise in Java development, with a strong understanding of Java 11+ and experience in building scalable backend systems. Experience in modernizing legacy systems, with a focus on optimizing performance, scalability, and cost-efficiency. Proficiency in CI/CD pipelines using tools like Jenkins, ensuring efficient delivery of high-quality software. Strong database expertise, including experience with relational and NoSQL databases, along with skills in database design, optimization, and management. Proficiency in Infrastructure as Code (IaC) tools such as Terraform or AWS CloudFormation. Nice to Have: we leverage the latest technologies, including the AI revolution. Experience with AI tools that enhance productivity is highly desired. What We Offer: Exciting Projects: We focus on industries like High-Tech, communication, media, healthcare, retail and telecom. Our customer list is full of fantastic global brands and leaders who love what we build for them. Collaborative Environment: You Can expand your skills by collaborating with a diverse team of highly talented people in an open, laidback environment — or even abroad in one of our global centers or client facilities! Work-Life Balance: GlobalLogic prioritizes work-life balance, which is why we offer flexible work schedules, opportunities to work from home, and paid time off and holidays. Professional Development: Our dedicated Learning & Development team regularly organizes Communication skills training(GL Vantage, Toast Master),Stress Management program, professional certifications, and technical and soft skill trainings. Excellent Benefits: We provide our employees with competitive salaries, family medical insurance, Group Term Life Insurance, Group Personal Accident Insurance , NPS(National Pension Scheme ), Periodic health awareness program, extended maternity leave, annual performance bonuses, and referral bonuses. Fun Perks: We want you to love where you work, which is why we host sports events, cultural activities, offer food on subsidies rates, Corporate parties. Our vibrant offices also include dedicated GL Zones, rooftop decks and GL Club where you can drink coffee or tea with your colleagues over a game of table and offer discounts for popular stores and restaurants!

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop, implement, and maintain verification environments using Verilog/SystemVerilog. Apply UVM methodology to build and enhance testbenches, ensuring thorough coverage of verification scenarios. Perform debugging and root-cause analysis of test failures to ensure design quality. Verify and validate AMBA protocols (AXI, AHB, APB) where applicable. Collaborate on ARM-based SoC verification tasks (preferred, but not mandatory). Leverage strong knowledge of digital design fundamentals to identify design and verification gaps. Create and maintain automation scripts (Perl, Tcl, Make, Shell scripting) to improve verification efficiency. Work closely with design, validation, and architecture teams to ensure timely closure of verification tasks. Skills Must have 8+yrs exp Strong verification skills with hands-on experience in Verilog and SystemVerilog. Proven expertise in UVM methodology, with solid experience in developing testbenches. Good debugging and problem-solving skills. Familiarity with AMBA protocols (AXI, AHB, APB) good to have. Strong foundation in digital design fundamentals. Proficiency in scripting languages (Perl, Tcl, Make, Shell scripting) for automation. Nice to have Exposure to ARM-based SoCs preferred but not mandatory.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop System Verilog/UVM-based testbenches for block-level and system-level verification. Write and execute UVM test cases to verify functional correctness of RTL designs. Perform detailed functional coverage and code coverage analysis, and drive coverage closure. Debug simulation failures, root-cause issues, and work closely with design and verification teams for resolution. Collaborate with cross-functional teams to ensure successful verification closure within project timelines. * Develop and maintain scripts using Python or other scripting languages for automation, regression management, and data analysis (optional but preferred). Apply working knowledge of standard bus protocols such as AXI, APB, UART, and IJTAG for testbench development and debugging. Document verification plans, test specifications, test reports, and maintain traceability. Skills Must have 4-6y exp SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Nice to have Experience with python or any other scripting language is a plus

Must to Have with hands on Experience vSphere vCenter , ESX vSAN BGP Aria ( Operations) Routing protocols VCF Implementation VPN & Switching VCF Migration Micro segmentation Good to Have HCX HCX Tanzu ALB ( Adv. Load balancing) VCF9 vSphere VSS, VDS Do Provide adequate support in architecture planning, migration & installation for new projects in own tower (platform/dbase/ middleware/ backup) Lead the structural/ architectural design of a platform/ middleware/ database/ back up etc. according to various system requirements to ensure a highly scalable and extensible solution Conduct technology capacity planning by reviewing the current and future requirements Utilize and leverage the new features of all underlying technologies to ensure smooth functioning of the installed databases and applications/ platforms, as applicable Strategize & implement disaster recovery plans and create and implement backup and recovery plans Manage the day-to-day operations of the tower Manage day-to-day operations by troubleshooting any issues, conducting root cause analysis (RCA) and developing fixes to avoid similar issues. Plan for and manage upgradations, migration, maintenance, backup, installation and configuration functions for own tower Review the technical performance of own tower and deploy ways to improve efficiency, fine tune performance and reduce performance challenges Develop shift roster for the team to ensure no disruption in the tower Create and update SOPs, Data Responsibility Matrices, operations manuals, daily test plans, data architecture guidance etc. Provide weekly status reports to the client leadership team, internal stakeholders on database activities w.r.t. progress, updates, status, and next steps Leverage technology to develop Service Improvement Plan (SIP) through automation and other initiatives for higher efficiency and effectiveness Team Management Resourcing Forecast talent requirements as per the current and future business needs Hire adequate and right resources for the team Train direct reportees to make right recruitment and selection decisions Talent Management Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness Build an internal talent pool of HiPos and ensure their career progression within the organization Promote diversity in leadership positions Performance Management Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below Employee Satisfaction and Engagement Lead and drive engagement initiatives for the team Track team satisfaction scores and identify initiatives to build engagement within the team Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team Exercise employee recognition and appreciation Mandatory Skills: Vmware VDI . Experience: 5-8 Years .

The SoC Development team at Sandisk is looking for highly motivated SoC Verification Engineers to join the talented team, contributing to cutting-edge controller development for high-performance SoCs used in industry-leading products. As a SoC Verification Engineer, you will play a crucial role in ensuring the quality and reliability of our SoC designs by developing verification test plans, executing test cases across multiple platforms, and collaborating with various teams to define verification strategies. You will have the opportunity to work on advanced verification environments, analyze functional coverage, and enhance verification efficiency while driving innovations in data storage solutions. Qualifications: - BE or MS degree in Electrical/Electronics Engineering or Computer Engineering, with 4-8 years of experience - Deep understanding of C, SystemVerilog UVM, and coverage-driven verification methodology - Knowledge of Chiplet Protocols like UCIe - Proficiency in C, Verilog, SystemVerilog, and UVM based verification - Experience in bus protocols such as AXI, AHB, APB, and bus interconnects - Strong debugging and problem-solving skills - Knowledge in various interfaces like PCIe, DP, UART, I2C, I2S, SPI, USB, SD - Experience working on processor-based SoCs (ARC/ARM/RISC) - Programming/Scripting skills in Python, Perl, TCL, and BASH - Interest in ASICs, SoCs, flash memory, and semiconductor components - Strong team player with excellent communication skills Joining Sandisk means being part of a team that solves complex verification challenges and drives innovations in data storage solutions. Your work will directly impact the performance and reliability of high-volume new age data solutions, consumer, and enterprise products. Together, we will push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions. Sandisk values diversity and believes that embracing various perspectives leads to the best outcomes for employees, customers, and communities. Sandisk is committed to providing opportunities to applicants with disabilities and ensuring a supportive and inclusive environment for all individuals.,

You should have a minimum of 1 year of experience and hold a B.E or M.Tech degree. Your role will involve working with Verilog, SystemVerilog, and UVM, designing and developing test plans, and creating test cases in UVM/SV,C. You should be comfortable working independently to develop Drive/Monitor code. It is essential for you to have knowledge of APB/AXI/AHB protocols, and familiarity with MIPI protocol would be an added advantage. Additionally, proficiency in Perl and Python is required. If you meet the requirements and are interested in the position, please send your resume to jobs@maxvytech.com with the job title you are applying for. The salary offered for this position is 3 LPA.,

You will be joining 7Rays Semiconductors, a company that specializes in providing end-to-end VLSI design solutions to help clients achieve execution excellence. The team of experts at 7Rays Semiconductors focuses on architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using cutting-edge technologies and methodologies. Building effective partnerships with clients, the company delivers high-quality solutions tailored to meet specific needs, showcasing a commitment to excellence and innovation in semiconductor design. Located in Bangalore, KA, this opportunity requires a minimum of 5 years of experience in the Emulation domain. As an Emulation Engineer/Validation Engineer, your responsibilities will include building emulation models from RTL for IP/SS or SOC, bringing up emulation models, developing content, and collaborating with RTL designers and Verification engineers to resolve emulation build issues. You will also work closely with customers to address emulation challenges and partner with vendors to resolve emulation build issues. Ideal candidates should hold a B.Tech/M.Tech in Electronics/VLSI or equivalent and be familiar with SV/UVM methodology. Candidates should have hands-on experience with Emulators such as Palladium, Veloce, Zebu, etc., and demonstrate proficiency in porting ASIC RTL on the Emulators and generating Emulation builds. Additionally, expertise in domains/functions including AXI, APB, AHB, SPI, I2C, UART, PCIe, USB, Ethernet, CXL, Ucie, C2C, D2D, DDR4/5/6, LPDDR3/4/5/6, and NoC/Interconnect verification is required. Desired activities that candidates should be involved in are HW-SW co-verification, Boot, Reset, Clock verification, Low Power Verification, Regression management and debug, as well as the development of Scoreboard, Checkers, and tracker. Proficiency in scripting languages like PERL and PYTHON is also beneficial for this role.,

At LeadSoc, we collaborate with renowned product companies in the Semicon, Telecom & Automotive sectors, focusing on VLSI Design, Embedded Systems, and Platform Software. If you are enthusiastic about tackling challenging assignments, we encourage you to reach out to us promptly! Engaging in a brief conversation with you will provide us with the opportunity to offer insights into the type of projects awaiting you. It will also help us understand your professional aspirations, facilitating the establishment of a meaningful connection and engagement. This position is based in Bangalore and requires 3 to 6 years of experience. **Technical Requirements:** - Proficiency in verification at SoC/Sub-system and block levels - Hands-on experience with ARM architecture, AMBA protocol (SoC and sub-system level) - Strong familiarity with UVM/OVM/SV/Verilog and C based verification methodology - Exposure to GLS/Power aware verification is advantageous - Working knowledge of protocols such as PCIe, DDRx, Ethernet, USB, AXI, AHB, APB, I2C, SPI - Proficient in RTL debugging and test automation scripting using TCL/Perl/Python - Experience in developing TB/test cases from scratch - Familiarity with industry-standard verification tools **Expectations from the Role:** - Effective communication and interpersonal skills, capable of working autonomously or within a team - Quick learner with the ability to thrive in a distributed work environment - Demonstrated ownership and punctuality in tasks If you meet these requirements and are ready to take on exciting challenges in the field, we look forward to hearing from you soon!,

Role & responsibilities- Must have exposure to SoC Verification Programming Languages- C, C++, System Verilog, UVM Protocols- PCIe, AMBA, Ahb, Apb, Axi Notice Period- Immediate to 30 Days

As a DDR Subsystem Architect at Arm, you will be responsible for designing the hardware architecture of LPDDR, DDR, HBM, and GDDR subsystems for cutting-edge SoC platforms across various market segments including mobile, automotive, datacenter, networking, and IoT. Your role will involve collaborating with SoC architects, business units, and customers to define DDR subsystem features and requirements, authoring architectural specifications, and working with IP vendors to ensure successful execution. You will utilize your deep understanding of DDR controller design, memory types, controller-to-PHY interface protocols, Arm bus protocols, and various features related to DDR subsystems. Your expertise will be crucial in debugging performance and functional issues, drafting design specifications, and supporting execution teams throughout the development process. Additionally, you will be expected to leverage your excellent communication skills to effectively collaborate with cross-functional teams. To excel in this role, you should possess a Bachelor's or Master's degree in Electrical or Computer Engineering along with a minimum of 10 years of experience in a senior development position. Your ability to work strategically, think innovatively, and contribute actively to ongoing projects will be key to your success in this dynamic and fast-paced environment. Joining the Solutions Engineering SoC architecture team at Arm will provide you with significant opportunities to shape the team's culture and drive future success. Arm values collaboration, creativity, innovation, personal development, and impact, and as a team member, you will be encouraged to embody these core behaviors in your work. As an integral part of the Arm team, you can expect a competitive salary range of $253,300-$342,700 per year, along with a total reward package that reflects the company's commitment to recognizing and rewarding individual contributions. Arm is dedicated to building extraordinary teams, and if you require any accommodations during the recruitment process, you can reach out to accommodations@arm.com for assistance. Arm's hybrid working approach is designed to support high performance and personal wellbeing, allowing teams to determine their own working patterns based on project requirements and personal needs. The company is committed to providing flexibility while adhering to local regulations, and adjustments can be made to accommodate individual circumstances. Arm promotes equal opportunities and is committed to fostering a diverse and inclusive work environment for all employees.,

You should have experience in Logic design and RTL coding, as well as SoC design and integration for complex SoCs. Proficiency in Verilog/System-Verilog and Multi Clock designs including Asynchronous interfaces is essential. Familiarity with ASIC development tools such as Lint and CDC is required. Knowledge of Synthesis and understanding of timing concepts is a plus. Experience with ECO fixes, formal verification, and AMBA protocols like AXI, AHB, and APB, along with SoC clocking/reset architecture is necessary. Strong communication skills, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills are expected. Your responsibilities will include understanding standards and specifications, developing architecture, documenting implementation details, hands-on work throughout the verification cycle, ensuring compliance with the latest methodologies, developing Verification IPs, defining Functional Coverage matrix and Comprehensive Test plan, managing regression and functional coverage closure, integrating and verifying DUT for IP delivery sign-off, leading a small team, and demonstrating hands-on experience in the complete verification cycle with strong verification concepts. You should have a strong knowledge of Verilog, SystemVerilog, and UVM, experience in UVM-based Verification IP development, familiarity with AMBA AXI/AHB/APB System buses, hands-on experience with PCIe/Eth/USB/DDR, expertise in System Verilog Assertions, scripting for automation, release processes, simulations, and regressions, and excellent written and oral communication skills. Leading the Verification IP development with junior engineers, exposure to the full verification cycle, and being a DV Engineer, Design Verification, or Verification Engineer are desirable skills and experiences.,

So, what’s the role all about? You are expected to be a professional automation engineer with a strong testing background and knowledge of building automated systems & tests both front-end UI, backend services and databases. You will be testing all aspect of a distributed system. How will you make an impact? Be part of a cross-functional, distributed Scrum team that develops and supports the product. Develop API, automation, and integration tests for cloud scale products Run manual tests and build automation test suites for regression and new features, checking data in application and databases, automating deployment and data generation. Maintain and expand automated testing framework and tests. Be involved in new features development, provide input on the correct behavior of the system, following and executing on team-specified “done” criteria. Supporting with customer integration testing What’s in it for you? Join an ever-growing, market disrupting, global company where the teams – comprised of the best of the best – work in a fast-paced, collaborative, and creative environment! As the market leader, every day at NiCE is a chance to learn and grow, and there are endless internal career opportunities across multiple roles, disciplines, domains, and locations. If you are passionate, innovative, and excited to constantly raise the bar, you may just be our next NiCEr! Have you got what it takes? Should have 8+ years of experience across automation tools Strong knowledge of Db and it’s concepts and working experience on database – SQL, schema, Query & Performance analysis Strong Knowledge and work experience of of AWS services – EC2, ASG, ECS, ALB, RDS, Performance insights & Cloudwatch Knowledge and experience on working on Playwright with Javascript Strong Knowledge and experience on debugging and triaging the logs to find out the root cause of issues/bugs Strong Experience in API / Web Services Testing and API Automation tools such as Postman Experience on creating UI & API automation frameworks and adopting the same for testing. Knowledge and experience on performance testing (UI & API). Strong Requirements and Business Analysis skills with good focus on attention for details.Strong Agile Software Project Management, Test Management Tools: Jira, TFS, Test Automation Tools: Playwright, Selenium, Type Script, Test Architect Knowledge of Continuous Integration Tools Jenkins Strong Ability to define and execute Test Suites/Test Cases Strong Strategic thinking and planning skills Well versed with AWS infrastructure. knowledge to host Automation framework in scalable AWS infrastructure. You will have an advantage if you also have: Experience in Gatling for Performance test Experience in GoLang Experience on Python and Shell Scripting Enjoy NiCE-FLEX! At NiCE, we work according to the NiCE-FLEX hybrid model, which enables maximum flexibility: 2 days working from the office and 3 days of remote work, each week. Naturally, office days focus on face-to-face meetings, where teamwork and collaborative thinking generate innovation, new ideas, and a vibrant, interactive atmosphere. Requisition Number: - 8305 Reporting into : Tech Manager Role Type : Individual Contributor